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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16308-1E
32-Bit RISC Microcontroller
CMOS
FR30 Series
MB91133/MB91F133
s DESCRIPTION
The MB91133/MB91F133, a standard single-chip microcontroller featuring various I/O resources and bus control mechanisms to incorporate the control required for high-performance high-speed CPU processes, is the core unit in the 32-bit RISC CPU (FR family) . This unit has the optimal specifications for incorporating applications that require high-performance CPU processing power by featuring peripheral I/O resources suitable for single-lens reflex cameras, digital video cameras, etc.
s FEATURES
1. CPU
* * * * * * * * * * * 32-bit RISC (FR30) , load/store architecture, 5-level pipeline Multi-purpose register : 32 bits x 16 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle Instructions for barrel shift, bit processing and inter-memory transfers : Instructions suited to loading purposes Function entry / exit instruction, multi load / store instruction of register details : High-level language handling instruction Register interlock function : Simplification of assembler description Branch instruction with delay slot : Reduction in overheads in case of branching Multiplier is built-in / supported at instruction level. Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles Interruption (saving PC and PS) : 6 cycles, 16 priority levels (Continued)
s PACKAGES
144-pin plastic FBGA 144-pin plastic LQFP
(BGA-144P-M01)
(FPT-144P-M08)
MB91133/MB91F133
(Continued)
2. Bus Interface
* * * * * 24-bit address output, 8/16-bit data input/output Basic bus cycle : 2 clock cycles Interface support for various memories Unused data and address pins can be used as input/output ports. Supports "little endian" mode
3. Built-in ROM
Mask device : 254 KB; FLASH device : 254 KB; EVA-FLASH device : 254 KB
4. Built-in RAM
Mask device : 8 KB; FLASH device : 8 KB; EVA-FLASH device : 8 KB
5. DMA Controller
This is a descriptor-type MA controller whose transfer parameters are arranged in the main memory. A maximum of 8 factors in total (internal and external) can be transferred. External factors are 3 channels.
6. Bit Search Module
Searches the first "1" / "0" change bit positions within 1 cycle from MSB in 1 word
7. Timer
* 16-bit reload timer x 5 channels * 16-bit OCU x 8 channels, ICU x 4 channels, free-run timer x 1 channel Output waveform adjusting function for AC motor waveforms is included in the above timer. * 8/16-bit up/down timer/counter (8-bit x 2 channels or 16-bit x 1 channel) External interruption and pin are shared for AIN and BIN. * 16-bit down count timer x 5 channels; can also be used as the UART baud rate timer * 16-bit PPG timer x 6 channels; out-pulse cycle / duty can be changed at random * 8-bit x 3 channels * * * * 10-bit x 8 channels Sequential conversion method (conversion time 5.0 s at 33 MHz) Setting for single conversion, scan conversion and repeat conversion is possible. Conversion starting function using hardware or software
8. D/A Converter
9. A/D Converter (Sequential comparison type)
10. Serial I/O
* UART x 5 channels; clock synchronous serial transfer with LSB / MSB switching function is possible for both. * Serial data output or serial lock output can be selected using push-pull / open-drain software. * 1 channel; shared input and pins of A/D converter.
11. Level Comparator Input 12. Clock Switching Function
* Base clock : Software can be used to select from two types of clock sources, namely 32 kHz and high-speed. * Gear function : Four types of settings (1 : 1, 1 : 2, 1 : 4, 1 : 8) can be set individually as the operating clock ratio to the basic clock per CPU and peripheral equipment.
2
MB91133/MB91F133
13. Interruption Controller
* External interruption input (total 24 channels) * With pull up pin control / standby return function : 4 channels (rising / falling / H level / L level settings are possible) * With pull up pin control / standby return function; AIN / BIN pins of the up/down counter are shared : 4 channels (rising / falling / H level / L level settings are possible) * With pull up pin controln : 16 channels (rising / falling / H level / L level settings are possible) * Internal interruption factor * Interruption / delay interruption by resource
14. Others
* Reset factors Power on reset, watchdog timer, software reset, external reset * Low power consumption mode Sleep/stop mode * Packages FBGA-144, LQFP-144 * CMOS technology (0.35 m) * Power Two power sources (5 V / 3 V) 1) 5 V system : 5 V 10% (A/D, D/A and level comparator included) 2) 3 V system : A) 3.0 V to 3.6 V : All functions guaranteed B) 2.7 V to 3.0 V : All functions guaranteed for single-chip mode of mask devices only
s PRODUCT LINEUP
MB91133 CLASSIFICATION RAM capacity CROM capacity FLASH capacity CRAM capacity Others MASK ROM device (mass production item) 6 KB 254 KB 2 KB Mass production MB91F133 FLASH ROM device (for evaluation) 6 KB 254 KB 2 KB Trial production MB91FV130 Piggy/EVA device (for evaluation / development) 6 KB 254 KB 2 KB Provided
3
MB91133/MB91F133
s PIN ASSIGNMENTS
* MB91FV130
(BOTTOM VIEW)
3 2 5 8 25 27 32 34 22 29 37 50 53 45 49 52 57 68 71 74
299 296 293 277 274 270 268 278 275 262 254 247 257 252 250 245 233 230 224 298 292 289 286 283 280 276 269 264 263 258 251 248 243 240 237 234 225 221 10 13 16 19 23 26 33 39 40 44 51 55 59 62 65 69 75 80 4 6 11 15 18 24 31 38 41 46 54 60 63 67 73 78 84 83 297 291 287 284 279 271 265 261 256 249 242 239 235 229 228 219 218 300 295 290 285 281 272 267 259 255 246 241 236 231 226 223 215 207 7 12 17 21 30 35 43 47 56 61 66 72 76 79 87 95 1 9 14 20 28 36 42 48 58 64 70 77 81 85 90 82 86 89 93 88 91 92 98 94 96 99 294 288 282 273 266 260 253 244 238 232 227 222 217 212 202 220 216 213 209 199 214 211 210 205 195 208 206 204 201 203 198 197 196 194 200 192 193 191 190 187 186 185 188 189 179 178 180 181 183 172 170 171 174 176 184 164 167 168 173 182 159 162 165 169 177 103 110 116 123 133 139 145 153 157 161 166 175 105 109 117 122 131 136 141 147 151 156 163 158 106 111 115 121 129 135 138 142 148 154 160 155
101 108 113 114 119 126 130 134 137 140 144 150 152 97 104 112 125 128 118 120 124 127 132 143 146 149
100 102 107
(PGA-299C-A01)
4
MB91133/MB91F133
* MB91F133/MB91133
(TOP VIEW)
14 13 12 11 10 9 8 7 6 5 4 3 2 1
108 110 111 115 118 121 125 128 132 135 138 142 143 144
107 109 112 114 117 120 124 129 133 136 139 141 1 2
106 105 113 116 119 122 126 127 134 137 140 5 4 3
102 103 104
99 100 101
96 97 98 95
92 93 91 94
89 88 90 87
85 84 86
82 81 83
79 78 80
75 76 77 68 65
74 73 69 67 64 61 57 52 48 45 42 40 37 35
72 71 70 66 63 60 56 53 49 46 43 39 38 36
59 123 130 131 58 51
62 55 54 50 47
15 8 6 7 11 9 10 14 12 13 18 16 17
22 19 21 20
23 26 25 24 29 28 27 32 31 30
44 41 33 34
A
B
C
D INDEX
E
F
G
H
J
K
L
M
N
P
(BGA-144P-M01)
5
6 * MB91F133/MB91133
MB91133/MB91F133
P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 VSS P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 VSS VCC5 P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 P60/A16/INT16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
(TOP VIEW)
(FPT-144P-M08)
P61/A17/INT17 P62/A18/INT18 P63/A19/INT19 P64/A20/INT20 P65/A21/INT21 P66/A22/INT22 P67/A23/INT23 VCC3 P80/RDY P81/BGRNT P82/BRQ P83/RD P84/WR0 P85/WR1 P86/CLK VSS PC0/INT0 PC1/INT1 PC2/INT2 PC3/INT3 PC4/AIN0/INT4 PC5/BIN0/INT5 PC6/AIN1/INT6 PC7/BIN1/INT7 PD0/INT8/TRG0 PD1/INT9/TRG1 PD2/INT10/TRG2 PD3/INT11/TRG3 PD4/INT12/TRG4 PD5/INT13/TRG5 PD6/DEOP2/INT14 PD7/ATG/INT15 PE0/ZIN0 PE1/ZIN1 PE2/IN0 PE3/IN1 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
MD2 MD1 MD0 VSS X1 X0 VCC3 X1A X0A VSS RST PL7/DACK2 PL6/DREQ2 PL5/DEOP1 PL4/DACK1 PL3/DREQ1 PL2/DEOP0 PL1/DACK0 PL0/DREQ0 PK7/AN7/CMP PK6/AN6 PK5/AN5 PK4/AN4 PK3/AN3 PK2/AN2 PK1/AN1 PK0/AN0 AVSS AVRL AVRH AVCC DAVC DAVS DA0 DA1 DA2
VCC5 PH0/SIN0 PH1/SOT0 PH2/SCK0 PI0/SIN1 PI1/SOT1 PI2/SCK1 PI3/SIN2 PI4/SOT2 PI5/SCK2 PJ0/SIN3 PJ1/SOT3 PJ2/SCK3 PJ3/SIN4 PJ4/SOT4 PJ5/SCK4 VCC3 VSS PG5/PPG5 PG4/PPG4 PG3/PPG3 PG2/PPG2 PG1/PPG1 PG0/PPG0 PF7/RTO7 PF6/RTO6 PF5/RTO5 PF4/RTO4 PF3/RTO3 PF2/RTO2 PF1/RTO1 PF0/RTO0 PE7/DTTI PE6/FRCK PE5/IN3 PE4/IN2
MB91133/MB91F133
s PIN NUMBERS LIST
* Device : MB91FV130 Package : PGA-299C-A01 No. Pin Name No. Pin Name No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 P20/D16 VSS OPEN P21/D17 VCC5 P22/D18 P23/D19 VSS P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 P40/A00 VCC5 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 VSS P47/A07 P50/A08 P51/A09 P52/A10 P53/A11 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 P54/A12 P55/A13 VCC5 P56/A14 P57/A15 P60/A16/INT16 P61/A17/INT17 P62/A18/INT18 P63/A19/INT19 P64/A20/INT20 P65/A21/INT21 P66/A22/INT22 P67/A23/INT23 P80/RDY VCC3 VSS P81/BGRNT P82/BRQ VCC5 P83/RD P84/WR0 P85/WR1 P86/CLK PL0/DREQ0 PL1/DACK0 PL2/DEOP0 PL3/DREQ1 PL4/DACK1 PL5/DEOP1 PL6/DREQ2 PL7/DACK2 N.C. N.C. VCC5 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Pin Name N.C. N.C. VSS N.C. N.C. VCC5 N.C. MD0 MD1 MD2 VCC3 VSS X0 X1 VCC5 RST N.C. ICLK ICS0 ICS1 ICS2 ICD0 ICD1 ICD2 ICD3 BREAK AVCC AVRH VSS AVRL AVSS PK0/AN0 PK1/AN1 PK2/AN2 No. 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 Pin Name PK3/AN3 VCC5 PK4/AN4 PK5/AN5 PK6/AN6 PK7/AN7/CMP DAVC DAVS DA0 VSS DA1 DA2 PH0/SIN0 PH1/SOT0 PH2/SCK0 PI0/SIN1 PI1/SOT1 PI2/SCK1 PI3/SIN2 PI4/SOT2 PI5/SCK2 PJ0/SIN3 VCC5 PJ1/SOT3 PJ2/SCK3 VSS VCC3 X0A X1A VSS PJ3/SIN4 PJ4/SOT4 PJ5/SCK4 PC0/INT0
(Continued)
7
MB91133/MB91F133
(Continued) No. Pin Name
137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 8 PC1/INT1 PC2/INT2 PC3/INT3 PC4/INT4/AIN0 PC5/INT5/BIN0 PC6/INT6/AIN1 VCC5 PC7/INT7/BIN1 PD0/INT8/TRG0 VSS PD1/INT9/TRG1 PD2/INT10/TRG2 VCC5 PD3/INT11/TRG3 PD4/INT12/TRG4 VSS PD5/INT13/TRG5
PD6/INT14/DEOP2
No. 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Pin Name PF5/RTO5 PF6/RTO6 PF7/RTO7 PG0/PPG0 PG1/PPG1 PG2/PPG2 VSS PG3/PPG3 PG4/PPG4 PG5/PPG5 N.C. N.C. N.C. N.C. VCC5 EXRAM TAD00 TAD01 TAD02 TAD03 VCC3 TAD04 TAD05 TAD06 TAD07 TAD08 TAD09 VSS TAD10 TAD11 VCC5 TAD12 TAD13 TAD14 TAD15 TCLK
No. 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244
Pin Name TAD14 TAD15 VCC3 TOE TCE1 TADSC TWR TDT00 TDT01 VSS TDT02 TDT03 VCC5 TDT04 TDT05 VSS TDT06 TDT07 TDT08 TDT09 TDT10 VCC5 TDT11 TDT12 VSS TDT13 TDT14 TDT15 TDT16 TDT17 TDT18 VCC3 TDT19 TDT20 TDT21 TDT22
No. 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280
Pin Name TDT23 TDT24 VSS TDT25 TDT26 TDT27 TDT28 TDT29 TDT30 VCC5 TDT31 TDT32 TDT33 TDT34 TDT35 TDT36 TDT37 VSS TDT38 TDT39 TDT40 TDT41 TDT42 TDT43 VCC3 TDT44 TDT45 TDT46 TDT47 TDT48 VCC5 TDT49 TDT50 VSS TDT51 TDT52
No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Pin Name TDT53 TDT54 TDT55 TDT56 TDT57 VCC3 TDT58 TDT59 TDT60 TDT61 TDT62 TDT63 VCC5 TDT64 TDT65 VSS TDT66 TDT67 VCC5 TDT68
VCC5 PD7/INT15/ATG PE0/ZIN0 VSS PE1/ZIN1 PE2/IN0 PE3/IN1 PE4/IN2 PE5/IN3 PE6/FRCK PE7/DTTI VCC3 PF0/RTO0 PF1/RTO1 PF2/RTO2 PF3/RTO3 PF4/RTO4 VCC5
MB91133/MB91F133
* Device : MB91F133/MB91133 LQFP FBGA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 B2 B1 C1 C2 C3 D2 D1 D3 E2 E1 E3 F2 F1 F3 G4 G2 G1 G3 H3 H1 H2 H4 J4 J1 J2 J3 K1 K2 K3 L1 L2 L3 M2 M1 N1 Pin Name P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 VSS P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 VSS VCC5 P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 Package : BGA-144P-M01/FPT-144P-M08 LQFP FBGA 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 P1 N2 P2 P3 N3 M3 N4 P4 M4 N5 P5 M5 N6 P6 M6 L7 N7 P7 M7 M8 P8 N8 L8 L9 P9 N9 M9 P10 N10 M10 P11 N11 M11 N12 P12 Pin Name P60/A16/INT16 P61/A17/INT17 P62/A18/INT18 P63/A19/INT19 P64/A20/INT20 P65/A21/INT21 P66/A22/INT22 P67/A23/INT23 VCC3 P80/RDY P81/BGRNT P82/BRQ P83/RD P84/WR0 P85/WR1 P86/CLK VSS PC0/INT0 PC1/INT1 PC2/INT2 PC3/INT3 PC4/AIN0/INT4 PC5/BIN0/INT5 PC6/AIN1/INT6 PC7/BIN1/INT7 PD0/INT8/TRG0 PD1/INT9/TRG1 PD2/INT10/TRG2 PD3/INT11/TRG3 PD4/INT12/TRG4 PD5/INT13/TRG5
PD6/DEOP2/INT14
LQFP FBGA 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 P13 P14 N13 N14 M14 M13 M12 L13 L14 L12 K13 K14 K12 J13 J14 J12 H11 H13 H14 H12 G12 G14 G13 G11 F11 F14 F13 F12 E14 E13 E12 D14 D13 D12 C13
Pin Name PE2/IN0 PE3/IN1 PE4/IN2 PE5/IN3 PE6/FRCK PE7/DTTI PF0/RTO0 PF1/RTO1 PF2/RTO2 PF3/RTO3 PF4/RTO4 PF5/RTO5 PF6/RTO6 PF7/RTO7 PG0/PPG0 PG1/PPG1 PG2/PPG2 PG3/PPG3 PG4/PPG4 PG5/PPG5 VSS VCC3 PJ5/SCK4 PJ4/SOT4 PJ3/SIN4 PJ2/SCK3 PJ1/SOT3 PJ0/SIN3 PI5/SCK2 PI4/SOT2 PI3/SIN2 PI2/SCK1 PI1/SOT1 PI0/SIN1 PH2/SCK0
PD7/ATG/INT15 PE0/ZIN0 PE1/ZIN1
(Continued)
9
MB91133/MB91F133
(Continued) LQFP FBGA
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 C14 B14 A14 B13 A13 B12 A12 C12 B11 A11 C11 B10 A10 C10 B9 A9 C9 D8 B8 A8
Pin Name PH1/SOT0 PH0/SIN0 VCC5 DA2 DA1 DA0 DAVS DAVC AVCC AVRH AVRL AVSS PK0/AN0 PK1/AN1 PK2/AN2 PK3/AN3 PK4/AN4 PK5/AN5 PK6/AN6 PK7/AN7/CMP
LQFP FBGA 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 C8 C7 A7 B7 D7 D6 A6 B6 C6 A5 B5 C5 A4 B4 C4 B3 A3 A2 A1
Pin Name PL0/DREQ0 PL1/DACK0 PL2/DEOP0 PL3/DREQ1 PL4/DACK1 PL5/DEOP1 PL6/DREQ2 PL7/DACK2 RST VSS X0A X1A VCC3 X0 X1 VSS MD0 MD1 MD2
10
MB91133/MB91F133
s PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pin name D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24/P30 D25/P31 D26/P32 D27/P33 D28P34 D29/P35 D30/P36 D31/P37 A00/P40 A01/P41 A02/P42 A03/P43 A04/P44 A05/P45 A06/P46 A07/P47 A08/P50 A09/P51 A10/P52 A11/P53 A12/P54 A13/P55 A14/P56 A15/P57 A16/INT16/P60 A17/INT17/P61 A18/INT18/P62 A19/INT19/P63 A20/INT20/P64 A21/INT21/P65 A22/INT22/P66 A23/INT23/P67 Circuit type Function
C
External data bus bits 16 to 23 Only valid for external bus 16-bit mode. Can be used as ports in single-chip and external bus 8-bit modes.
C
External data bus bits 24 to 31 Can be used as ports in single-chip mode.
F
External address bus bits 0 to 15 Valid for external bus mode. Can be used as ports in single-chip mode.
O
External address bus bits 16 to 23 [ INT16 to 23 ] are external interruption request inputs 16 to 23. These inputs are always used when dealing with external interruptions is permitted, so output by ports should be stopped except when carried out intentionally. Can be used as ports when address bus and external interruption request input are not used. External RDY input This function is valid when external RDY input is permitted. "0" is input if the bus cycle being executed is not completed. Can be used as a port when the external RDY input is not used.
45
RDY/P80
C
(Continued)
11
MB91133/MB91F133
Pin No.
Pin name
Circuit type
Function External bus open reception output This function is valid when external bus open reception output is permitted. "L" is output if the external bus is opened. Can be used as a port when the external bus open reception output is prohibited. External bus open request input This function is valid when external bus open request input is permitted. "1" is input if the external bus requests to be opened. Can be used as a port when the external bus open request input is not used. External bus read strobe output This function is valid when external bus read strobe output is permitted. Can be used as a port when the external bus read strobe output is prohibited. External bus write strobe output This function is valid in external bus mode. Can be used as a port in single-chip mode. External bus write strobe output This function is valid in external bus mode and with 16-bit buses. Can be used as a port in single-chip mode or with external 8-bit bus. System clock output Outputs the same clock frequency as the external bus operation. Can be used as a port when it is not otherwise used. External interruption request inputs 0 to 3 These inputs are always used when dealing with external interruptions is permitted, so output by ports should be stopped except when carried out intentionally. Can be used to reset standby as input is permitted in this port under standby status.Can be used as ports when external interruption request input is not used. External interruption request inputs 4 to 7 These inputs are always used when dealing with external interruptions is permitted, so output by ports should be stopped except when carried out intentionally. Can be used to reset standby as input is permitted in these ports under standby status.
46
BGRNT/P81
F
47
BRQ/P82
C
48
RD/P83
F
49
WR0/P84
F
50
WR1/P85
F
51
CLK/P86
F
53 54 55 56
INT0/PC0 INT1/PC1 INT2/PC2 INT3/PC3
H
57 58 59 60
AIN0/INT4/PC4 BIN0/INT5/PC5 AIN1/INT6/PC6 BIN1/INT7/PC7
H [ AIN, BIN ] Up/down timer input This input is always used when input is permitted, so output by ports should be stopped except when carried out intentionally. Can be used as a port when external interruption request input and up/down timer input are not used.
(Continued)
12
MB91133/MB91F133
Pin No.
Pin name
Circuit type
Function External interruption request inputs 8 to 15 These inputs are always used when dealing with external interruptions is permitted, so output by ports should be stopped except when carried out intentionally. [ TRG0 to 5 ] These are external trigger inputs for PPG timers. [ DEOP2 ] DMA external transfer termination output This function is valid when external transfer termination output specification of the DMA controller is permitted. [ ATG ] A/D converter external trigger input These inputs are always used when they are selected as A/D initiation factors, so output by ports should be stopped except when carried out intentionally. Can be used as ports when not otherwise used. Up/down timer input These inputs are always used when input is permitted, so output by ports should be stopped except when carried out intentionally. Can be used as ports when up/down timer input is not used. Input capture input This function is valid when input capture activates input. Can be used as ports when input capture input is not used. External clock input pin of free-run timer Can be used as a port when external clock input of free-run timer is not used. RTOn pin level fixed input Invalid when input is permitted in the waveform generation area. Can be used as a port when RTOn pin level fixed input is not used.
61 62 63 64 65 66 67 68
TRG0/INT8/PD0 TRG1/INT9/PD1 TRG2/INT10/PD2 TRG3/INT11/PD3 TRG4/INT12/PD4 TRG5/INT13/PD5 DEOP2/INT14/PD6 ATG/INT15/PD7
O
69 70 71 72 73 74 75
ZIN0/PE0 ZIN1/PE1 IN0/PE2 IN1/PE3 IN2/PE4 IN3/PE5 FRCK/PE6
O
F
F
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 111 110 109
DTTI/PE7 RTO0/PF0 RTO1/PF1 RTO2/PF2 RTO3/PF3 RTO4/PF4 RTO5/PF5 RTO6/PF6 RTO7/PF7 PPG0/PG0 PPG1/PG1 PPG2/PG2 PPG3/PG3 PPG4/PG4 PPG5/PG5 DA0 DA1 DA2
F
F
Output compare event pins/waveform output pins in the waveform generation area Can be used as ports when specification of the output compare event pin/waveform output pin of the waveform generation area is prohibited.
F
PPG timer output This function is valid when output specification of the PPG timer is permitted. Can be used as ports when output specification of the PPG timer is prohibited. D/A converter output This function is valid when output specification of the D/A converter is permitted.
(Continued)
13
MB91133/MB91F133
Pin No.
Pin name
Circuit type
Function UART0 data input This input is always used when UART0 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART0 data input is not used. UART0 data output This function is valid when UART0 data output specification is permitted. Can be used as a port when UART0 data output specification is prohibited. UART0 clock input/output This function is valid when UART0 clock output specification is permitted. Can be used as a port when UART0 clock output specification is prohibited. UART1 data input This input is always used when UART1 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART1 data input is not used. UART1 data output This function is valid when UART1 data output specification is permitted. Can be used as a port when UART1 data output specification is prohibited. UART1 clock input/output This function is valid when UART1 clock output specification is permitted. Can be used as a port when UART1 clock output specification is prohibited. UART2 data input This input is always used when UART2 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART2 data input is not used. UART2 data output This function is valid when UART2 data output specification is permitted. Can be used as a port when UART2 data output specification is prohibited. UART2 clock input/output This function is valid when UART2 clock output specification is permitted. Can be used as a port when UART2 clock output specification is prohibited. UART3 data input This input is always used when UART3 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART3 data input is not used. UART3 data output This function is valid when UART3 data output specification is permitted. Can be used as a port when UART3 data output specification is prohibited.
107
SIN0/PH0
P
106
SOT0/PH1
P
105
SCK0/PH2
P
104
SIN1/PI0
P
103
SOT1/PI1
P
102
SCK1/PI2
P
101
SIN2/PI3
P
100
SOT2/PI4
P
99
SCK2/PI5
P
98
SIN3/PJ0
P
97
SOT3/PJ1
P
(Continued)
14
MB91133/MB91F133
Pin No.
Pin name
Circuit type
Function UART3 clock input/output This function is valid when UART3 clock output specification is permitted. Can be used as a port when UART3 clock output specification is prohibited. UART4 data input This input is always used when UART4 activates input, so output by ports should be stopped except when carried out intentionally. Can be used as a port when UART4 data input is not used. UART4 data output This function is valid when UART4 data output specification is permitted. Can be used as a port when UART4 data output specification is prohibited. UART4 clock input/output This function is valid when UART4 clock output specification is permitted. Can be used as a port when UART4 clock output specification is prohibited.
96
SCK3/PJ2
P
95
SIN4/PJ3
P
94
SOT4/PJ4
P
93
SCK4/PJ5
P
118 119 120 121 122 123 124 125
AN0/PK0 AN1/PK1 AN2/PK2 AN3/PK3 AN4/PK4 AN5/PK5 AN6/PK6 CMP/AN7/PK7
A/D converter analog input This is valid when the AICK register specification is analog input. N [ CMP ] level comparator input Can be used as ports when A/D converter analog input is not used.
126
DREQ0/PL0
F
DMA external transfer request input This input is always used if selected as the transfer factor for the DMA controller, so output by ports should be stopped except when carried out intentionally. Can be used as a port when DMA external transfer request input is not used. DMA external transfer request reception output This function is valid when external transfer request reception output specification of the DMA controller is permitted. Can be used as a port when transfer request reception output specification of the DMA controller is prohibited. DMA external transfer termination output This function is valid when external transfer termination output specification of the DMA controller is permitted. DMA external transfer request input This input is always used if selected as the transfer factor for the DMA controller, so output by ports should be stopped except when carried out intentionally. Can be used as a port when DMA external transfer request input is not used.
127
DACK0/PL1
F
128
DEOP0/PL2
F
129
DREQ1/PL3
F
(Continued)
15
MB91133/MB91F133
(Continued)
Pin No. Pin name Circuit type Function DMA external transfer request reception output This function is valid when external transfer request reception output specification of the DMA controller is permitted. Can be used as a port when transfer request reception output specification of the DMA controller is prohibited. DMA external transfer termination output This function is valid when external transfer termination output specification of the DMA controller is permitted. DMA external transfer request input This input is always used if selected as the transfer factor for the DMA controller, so output by ports should be stopped except when carried out intentionally. Can be used as a port when DMA external transfer request input is not used. DMA external transfer request reception output This function is valid when external transfer request reception output specification of the DMA controller is permitted. Can be used as a port when transfer request reception output specification of the DMA controller is prohibited. External reset input Oscillation pin for low-speed clock (32 kHz) Oscillation pin for high-speed clock (16.5 MHz) Mode pins Basic MCU operation mode is set by these pins. They should be directly connected to VCC or VSS for use. Ground pin of D/A converter (connected to analog ground) Power pin of D/A converter Power pin for A/D converter Reference voltage pin for A/D converter (high electric potential side) When this pin is turned on/off, AVRH or more electric potential must be supplied to VCC. Reference voltage pin for A/D converter (low electric potential side) Ground pin for A/D converter (connected to analog ground) 5 V power of digital circuit Power must be connected to all VCC5 pins for use. 3 V power of digital circuit Power must be connected to all VCC3 pins for use. Ground level of digital circuit
130
DACK1/PL4
F
131
DEOP1/PL5
F
132
DREQ2/PL6
F
133
DACK2/PL7
F
134 136 137 139 140 142 143 144 112 113 114 115
RST X0A X1A X0 X1 MD0 MD1 MD2 DAVS DAVC AVCC AVRH
B K A G
116 117 27, 108 44, 92 138 9, 26, 52, 91, 135, 141
AVRL AVSS VCC5 VCC3 VSS

Note : In most of the above pins, the input/output of the I/O ports and resources are multiplexed, such as xxxx/Pxx. If the output from ports and resources of those pins compete with each other, the resource is given priority. 16
MB91133/MB91F133
s INPUT/OUTPUT CIRCUIT TYPES
Type
X1 Xout
Circuit
Remarks * High-speed oscillation circuit (16.5 MHz) Oscillation feedback resistance = approximately 1 M 3 V CMOS level input
A
X0
Standby control signal
* With pull up resistance CMOS level input Pull-up resistance value = approximately 25 k (Typ.) B
Digital input
* CMOS level input/output pin
Pout
CMOS level output CMOS level input (with standby control) IOL = 4 mA
C
R
Nout
CMOS input Standby control
* CMOS hysteresis input/output pin
Pout
CMOS level output CMOS hysteresis input (with standby control) IOL = 4 mA
F
R
Nout
Hysteresis input Standby control
(Continued)
17
MB91133/MB91F133
Type
Circuit
Remarks * CMOS level input pin CMOS level input (without standby control)
G
R Digital input
IOL = 4 mA
Pull-up control R Pout
* CMOS hysteresis input/output pin with pull- up control CMOS level output CMOS hysteresis input (without standby control) Pull-up resistance value = approximately 50 k (Typ.) IOL = 4 mA * Clock oscillation circuit (32 kHz)
H
Nout R Hysteresis input
X1A Xout
K
X0A
Oscillation feedback resistance = approximately 4.5 M/3 V 3 V CMOS level input
Standby control signal
* Analog/CMOS level input/output pin
Pout
Nout
N
R CMOS input Standby control Analog input
CMOS level output CMOS level input (with standby control) Analog input (Analog input is valid when bit dealt by AIC is "1".) IOL = 4 mA
(Continued)
18
MB91133/MB91F133
(Continued) Type
Circuit
Pull-up control
Remarks * CMOS hysteresis input/output pin with pull-up control CMOS level output CMOS hysteresis input (with standby control) Pull-up resistance value = approximately 50 k (Typ.) IOL = 4 mA
R
Pout
O
R
Nout
Hysteresis input Standby control
Pull-up control Open-drain control
* CMOS hysteresis input/output pin with pull-up control CMOS level output (with open-drain control) CMOS hysteresis input (with standby control) Pull-up resistance value = approximately 50 k (Typ) IOL = 4 mA
R
P
R
Nout
Hysteresis input Standby control
19
MB91133/MB91F133
s HANDLING DEVICES
1. Points to Note on Handling Devices
(1) Latch-up prevention Latch-up may occur by CMOS IC if a voltage in excess of VCC5 or lower than VSS is applied to the input/output pins, or if the voltage exceeds the rating between VCC5 and VSS. If latch-up occurs, the electrical current increases significantly and may destroy certain components due to excessive heat, so great care must be taken to ensure that the maximum rating is not exceeded during use. (2) Handling Pins * Handling unused pins Input pins that are not used should be pulled up or down as they may cause erroneous operations if left open. * Handling N.C. pins N.C. pins must be opened for use. * Handling output pins Excessive electric current may flow if the output pin is shorted by the power source or other output pins, or connected to large loads. If such status is prolonged, the device is liable to be damaged, so great care must be taken to ensure that the usage volume does not exceed the maximum rating. * Mode pins (MD0 to MD2) Those pins must be directly connected to VCC5 or VSS for use. Pattern lengths between VCC5 or VSS and each mode pin on the printed-circuit board should be arranged to be as short as possible to prevent the test mode from being erroneously turned on due to noise, and they should be connected with low impedance. * Power pins When there are a number of VCC5/VCC3/VSS, those whose electrical potential must be the same within the device are connected to prevent erroneous operation such as latch-up for device design purposes, but those must be externally connected to a power source and earthed to follow the general output current standard and prevent erroneous operation of strobe signals due to increased ground level and reduction in unnecessary radiation. Care must also be taken to ensure that they are connected to the VCC5/VSS or VCC3/VSS of this device at the lowest possible impedance from the source of the electrical current supply. Furthermore, it is recommended that a ceramic capacitor of around 0.1 F be used to connect the VCC5 and VSS, or VCC3 and VSS near the device as a bypass capacitor. * Crystal oscillation circuits Noise near the X0, X1, X0A or X1A pins can cause erroneous operation. The printed-circuit board must be designed so that the X0, X1, X0A and X1A pins, crystal oscillator (or ceramic oscillator) and bypass capacitor to the ground can be arranged as close as possible. Also, a printed-circuit board with grounded artwork enclosing the X0, X1, X0A and X1A pins is strongly recommended to ensure stable operation.
20
MB91133/MB91F133
(3) Points to note on usage * External reset input "L" level should be input to the RST pin, which is required for at least five machine cycles to ensure that the internal status is reset. * Oscillation pin Oscillation pin is 3 V CMOS input level. * External clock Use with an external clock is prohibited. A crystal (or ceramic) oscillator should be used. * Analog Power The AVCC should always be used at the same electric potential as VCC5. If the VCC5 is larger than the AVCC, electricity may flow through pins AN 0 to AN 7. * Points to note for using level comparator When the level comparator is used, a reference current (IR) flows even though it is stopped. The stop mode must be turned on after prohibiting action of the level comparator.
2. Points to Note on Turning On Power
* RST pin handling The RST pin must be started from "L" level when the power is turned on, and when the power is adjusted to the VDD level, it should be changed to the "H" level after being left on for at least 5 cycles of the internal operation clock. * Original oscillation input The clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on. * Power on reset "Power on reset" must be executed if power is turned on, but the power voltage falls below the guaranteed operating temperature and power is turned on again. * Order for turning on power Power should be turned on in the following order. VCC3 VCC5 AVCC AVRH The opposite order should be used when turning off.
21
MB91133/MB91F133
s BLOCK DIAGRAM
FR30 CPU UART x 5 ch RAM 6 Kbyte DREQ0 toDREQ 2 DACK0 toDACK 2 DEOP0 to DEOP2
15
SIN0 to SIN4 SOT0 to SOT4 SCK0 to SCK4
DMAC 8 ch
9
Reload timer x 5 ch
Resource Bus Controller
8 bit 3 output D/A converter
5
DA0 toDA2 DAVC, DAVS
Bus Converter A23 to A00 D31 to D16 RD WR1, WR0 RDY BRQ BGRNT CLK
47
6 6
PPG0 to PPG5 TRG0 to TRG5
External Bus Controller
RAM 2 Kbyte
16 bit PPG x 6 ch
Multi-Function Timer IN0 to IN3
ROM 254 Kbyte 16 bit ICU x 4 ch Interrupt Controller 16 bit FRT
4
FRCK RTO0 (U) RTO1 (X) RTO2 (V) RTO3 (Y) RTO4 (W) RTO5 (Z) RTO6 RTO7 DTTI
X0, X1, X0A, X1A RST MD0 to MD2 AIN0, 1 BIN0, 1 ZIN0, 1
Clock Generator
8
Up/Down counter x 2 ch
6
16 bit OCU x 8 ch INT0 to INT23 () 24 ch external interrupt
24
AN0 to AN7 AVRH, AVRL AVCC, AVSS CMP (AN7)
10 bit 8 input A/D converter
12
Waveform Generator
level comparator
* : INT23 to INT16 share pins with A23 to A16 * : INT15 shares pins with ATG * : INT14 shares pins with DEOP2 * : INT13 to INT8 share pins with TRG5 to TRG0 * : INT7 to INT4 share pins with AIN0, BIN0, AIN1 and BIN1 The total number of above pins is 133. The remainder (144 - 133 = 11 pins) are VCC5 , VCC3 and VSS.
22
MB91133/MB91F133
s CPU
1. Memory Space
The FR series has 4 Gbytes (232 addresses) of logic address space which the CPU accesses linearly. * Memory Map
External ROM external bus mode 0000 0000H I/O 0000 0400H I/O 0000 0800H Access is prohibited 0000 1000H Built-in RAM 6 KB 0000 2800H Access is prohibited 0001 0000H
Internal ROM external bus mode I/O
Single-chip mode Direct Madressing area Refer to "I/O MAP"
I/O
I/O
I/O
Access is prohibited
Access is prohibited
Built-in RAM 6 KB
Built-in RAM 6 KB
Access is prohibited
Access is prohibited 0001 0000H
External area External area Built-in RAM 2KB Built-in ROM 254KB External area FFFF FFFFH
Access is prohibited Built-in RAM 2KB
000C 0000H
000C 0800H Built-in ROM 254KB Access is prohibited FFFF FFFFH
010 0000H
* : It is impossible to access the external area on single-chip mode. When accessing the external area, select the internal ROM external bus mode.
23
MB91133/MB91F133
2. Registers
There are two types of multi-purpose registers in the FR family. One is a dedicated purpose register that exists within the CPU and the other is a multi-purpose register that exists in the memory. * Dedicated Registers Program Counter (PC) Program Status (PS) Table Base Register (TBR)
Return Pointer (RP) System Stuck Pointer (SSP) User Stuck Pointer (USP) Multiplication and Division Results Resister (MDH/MDL) : 32-bit length; act as registers for multiplication and division.
: 32-bit length; indicates instruction storage position. : 32-bit length; stores register pointers and condition codes. : Holds the starting address of the vector table to be used for Exception, Interruption and Trapping (EIT) . : Holds the address to return to from the sub-routine. : Indicates the system stuck position. : Indicates the user's stuck position.
32 bit PC
Program Counter
Initial values XXXX XXXXH
(Undecided)
PS
Program Status Table Base Register Return Pointer System Stuck Pointer User Stuck Pointer 000F FC00H XXXX XXXXH 0000 0000H XXXX XXXXH XXXX XXXXH XXXX XXXXH (Undecided) (Undecided) (Undecided) (Undecided)
TBR
RP
SSP
USP
MDH MDL
Multiplication and Division Results Resister
* Program Status (PS) PS is the register that holds the program status and is classified into three categories, namely, Condition Code Register (CCR) , System Condition Code Register (SCR) and Interruption Level Master Register (ILM) .
31 PS
20
19
18
17
16
10 D1
9 D0 SCR
8 T
7
6
5 S
4 I
3 N
2 Z
1 V
0 C
ILM4 ILM3 ILM2 ILM1 ILM0 ILM
CCR
24
MB91133/MB91F133
* Condition Code Register (CCR) S flag : Specifies the stuck pointer to be used as R15. I flag : Controls permission and prohibition of user interruption requests. N flag : Indicates codes when computation results are defined as integers that are expressed in complements of 2. Z flag : Indicates whether or not a result of the computation is "0" . V flag : Operands used for computation are defined as integers expressed in complements of 2, and indicate whether or not an overflow is generated as a result of the computation. C flag : Indicates whether carrying or borrowing is generated from the highest bit as a result of the computation. * System Condition Code Register (SCR) T flag : Specifies whether or not the step trace trap will be valid. * Interruption Level Mask Register (ILM) ILM4 to ILM0 : Holds the interruption level mask values, and those values that are held by the ILM are used for the level mask. Interruption requests can be accepted only when the interruption levels handled within the interruption requests to be input into the CPU are stronger than the levels shown by the ILM. ILM4 0 0 1 ILM3 0 1 1 ILM2 0 0 1 ILM1 0 0 1 ILM0 0 0 1 Interruption level 0 15 31 Weak Strength Strong
25
MB91133/MB91F133
s MULTI-PURPOSE REGISTERS
The multi-purpose registers are CPU registers R0 to R15 which are used as accumulators for various computations and memory access pointers (fields that indicate the address) . * Register bank configuration
32-bit
Initial value XXXX XXXXH
R0 R1
R12 R13 R14 R15
AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer)
XXXX XXXXH 0000 0000H
Special purposes are assumed for the following 3 of the 16 registers. Thus, some instructions are emphasized. R13 : Virtual accumulator (AC) R14 : Frame Pointer (FP) R15 : Stack Pointer (SP) Initial values for R0 to R14 on resetting are unspecified. The initial value of R15 will be 0000 0000H (SSP value) .
26
MB91133/MB91F133
s MODE SETTING
1. Pins
* Mode pins and set mode Mode pins Mode name MD2 MD1 MD0 0 0 0 0 1 0 0 1 1 0 1 0 1 External vector mode 0 External vector mode 1 Internal vector mode Reset vector access areas External External Internal External data bus width 8-bit 16-bit (Mode register) Bus modes External ROM external bus mode Setting is prohibited Single chip mode Usage is prohibited
2. Register
Mode register (MODR) and set mode Address 0000 07FFH Initial value Access XXXX XXXXB W
M1
M0
*
*
*
*
*
*
Bus mode set bit
W : Write only X : Undecided * : "0" should always be written for bits other than M1 and M0.
* Bus mode set bit and its functions M1 M0 0 0 1 1 0 1 0 1 Single chip mode
Functions
Remarks
Internal ROM external bus mode External ROM external bus mode Setting is prohibited
27
MB91133/MB91F133
s I/O MAP
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 000038H 00003CH 000040H ADCR TMRLR TMRLR PDRF PDRJ LVLC SSR0 SSR1 SSR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) PDRE PDRI (R/W) (R/W) PDR3 Register +0 (R/W) PDR2 PDR6 XXXXXXXX +1 (R/W) (R/W) PDR5 (R/W) XXXXXXXX XXXXXXXX PDRD PDRH PDRL SCR0 SCR1 SCR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) PDRC PDRG PDRK SMR0 SMR1 SMR2 (R) (R/W) (R) (R/W) ADCS0 (R) (R/W) Reload Timer 2 (R/W) Reload Timer 1 Reload Timer 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) XXXXXXXX +2 PDR4 PDR8 (R/W) (R/W) Port Data Register +3 Block
XXXXXXXX - XXXXXXX
XXXXXXXX - - XXXXXX XXXX 0 0 0 0 0 0 0 0 1 -00 0 0 0 0 1 -00 0 0 0 0 1 -00 TMRLR
XXXXXXXX - - XXXXXX
SIDR0/SODR0 (R/W)
XXXXXXXX - - - - - XXX XXXXXXXX 00000100 00000100 00000100 TMR TMCSR
XXXXXXXX - - XXXXXX XXXXXXXX 0 0 0 0 0-0 0 0 0 0 0 0-0 0 0 0 0 0 0-0 0 Level Comparator UART0 UART1 UART2
XXXXXXXX
SIDR1/SODR1 (R/W)
XXXXXXXX
SIDR2/SODR2 (R/W)
XXXXXXXX (W)
XXXXXXXX XXXXXXXX (W)
XXXXXXXX XXXXXXXX ----0000 0 0 0 0 0 0 0 0 TMR TMCSR XXXXXXXX XXXXXXXX ----0000 0 0 0 0 0 0 0 0
XXXXXXXX XXXXXXXX (R/W) (W)
ADCS1
(R/W)
0 0 1 0 1 - XX XXXXXXXX XXXXXXXX XXXXXXXX
00000000 TMR TMCSR
00000000
A/D Converter (Sequential type)
XXXXXXXX XXXXXXXX ----0000 0 0 0 0 0 0 0 0
(Continued)
28
MB91133/MB91F133
Address 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H
Register +0 IPCP1 IPCP3 ICS23 +1 (R) (R) (R/W) +2 IPCP0 IPCP2 ICS01 +3 (R) (R) (R/W)
Block
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 OCCP1 OCCP3 OCCP5 OCCP7 OCS32 OCS76 TCDT SSR3 SSR4 CDCR1 CDCR3 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 Reserved OCCP0 OCCP2 OCCP4 OCCP6 OCS10 OCS54 TCCS SCR3 SCR4 CDCR0 CDCR2 CDCR4 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) SMR3 SMR4 (R/W) (R/W) 16-bit OCU 16-bit ICU
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXX 0 0 0 0 0 0 0 0 0 XX 0 0 XXX 0 0 0 0 0 0 0 0 0 XX 0 0 00000000 00000000
SIDR3/SODR3 (R/W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXX 0 0 0 0 0 0 0 0 0 XX 0 0 XXX 0 0 0 0 0 0 0 0 0 XX 0 0 0------- 0 0 0 0 0 0 0 0 00000100 00000100 0 ---0 0 0 0 0 ---0 0 0 0 0 ---0 0 0 0 0 0 0 0 0-0 0 0 0 0 0 0-0 0 Communication Pre-scalar 16-bit Free-run Timer UART3 UART4
0 0 0 0 1 0 00 0 0 0 0 1 0 00 0 ---0 0 0 0 0 ---0 0 0 0
XXXXXXXX
SIDR4/SODR4 (R/W)
XXXXXXXX
(Continued)
29
MB91133/MB91F133
Address 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H to 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH PCRJ OCRJ EIRR0 RCR1
Register +0 (W) (R/W) (R/W) RCR0 CCRL0 CCRL1 00000000 CCRH0 CCRH1 00000000 -0 0 0 0 0 0 0 +1 (W) (R/W) (R/W) 00000000 -0 0 0 1 0 0 0 -0 0 0 1 0 0 0 (R/W) ENIR0 (R/W) EIRR1 (R/W) ENIR1 (R/W) +2 UDCR1 (R) 00000000 +3 UDCR0 CSR0 CSR1 (R) (R/W) (R/W) 00000000 00000000 00000000
Block
8-/16-bit U/D Counter
Reserved
00000000 ELVR0 EIRR2 (R/W)
00000000 (R/W) ENIR2 (R/W)
00000000 ELVR1
00000000 (R/W) Ext Int
00000000 00000000 00000000 ELVR2 00000000 (R/W) DACR2 DADR2 (R/W) TMRR1 SIGCR (R/W) (R/W) (R/W) (R/W)
00000000 00000000 DACR1 DADR1 DTCR0 DTCR2 (R/W) (R/W) (R/W) (R/W) DACR0 DADR0 TMRR0 TMRR2 (R/W) (R/W) (R/W) (R/W)
00000000 00000 000 DTCR1 -------0 XXXXXXXX XXXXXXXX 00000000 (R/W) (R/W) PCRE PCRI OCRI (R/W) (R/W) (R/W) PCRD PCRH OCRH (R/W) (R/W) (R/W) -------0 XXXXXXXX 00000000 00000000
-------0 XXXXXXXX XXXXXXXX XXXXXXXX
D/A Converter
00000000
Waveform Generator
Reserved PCRC (R/W) Pull-up Control
------0 0 --0 0 0 0 0 0 --0 0 0 0 0 0
00000000 -----0 0 0 -----0 0 0
00000000 AICK (R/W)
--0 0 0 0 0 0 --0 0 0 0 0 0
Open-drain Control Analog Input Control
00000000
(Continued)
30
MB91133/MB91F133
Address 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H 00010CH DDRF DDRJ
Register +0 (R/W) (R/W) DDRE DDRI 00000000 --0 0 0 0 0 0 GCN1 PTMR0 PDUT0 PTMR1 PDUT1 PTMR2 PDUT2 PTMR3 PDUT3 PTMR4 PDUT4 PTMR5 PDUT5 +1 (R/W) (R/W) DDRD DDRH DDRL 00000000 --0 0 0 0 0 0 (R/W) (R) (W) (R) (W) (R) (W) (R) (W) (R) (W) (R) (W) +2 (R/W) (R/W) (R/W) DDRC DDRG DDRK GCN2 (W) PCNL0 (W) PCNL1 (W) PCNL2 (W) PCNL3 (W) PCNL4 (W) PCNL5 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 00000000 -----0 0 0 00000000 PCSR0 PCNH0 (R/W) +3 (R/W) (R/W) (R/W) (R/W) 00000000 --0 0 0 0 0 0 00000000 00000000
Block
Data Direction Register
00110010 00010000 11111111 11111111 XXXXXXXX XXXXXXXX 11111111 11111111 XXXXXXXX XXXXXXXX 11111111 11111111 XXXXXXXX XXXXXXXX 11111111 11111111 XXXXXXXX XXXXXXXX 11111111 11111111 XXXXXXXX XXXXXXXX 11111111 11111111 XXXXXXXX XXXXXXXX
PPG ctl
XXXXXXXX XXXXXXXX 0000000PCSR1 PCNH1 (R/W) 00000000
PPG0
XXXXXXXX XXXXXXXX 0000000PCSR2 PCNH2 (R/W) 00000000
PPG1
XXXXXXXX XXXXXXXX 0000000PCSR3 PCNH3 (R/W) 00000000
PPG2
XXXXXXXX XXXXXXXX 0000000PCSR4 PCNH4 (R/W) 00000000
PPG3
XXXXXXXX XXXXXXXX 0000000PCSR5 PCNH5 (R/W) 00000000
PPG4
XXXXXXXX XXXXXXXX 000000000000000
PPG5
(Continued)
31
MB91133/MB91F133
Address 000110H 000114H 000118H 00011CH 000120H to 0001FCH 000200H 000204H 000208H 00020CH 000210H to 0003ECH 0003F0H 0003E4H 0003F8H 0003FCH 000400H 000404H 000408H ICR00 ICR04 ICR08
Register +0 TMRLR +1 (W) +2 TMR TMCSR (W) TMR TMCSR +3 (R) (R/W) (R) (R/W)
Block
XXXXXXXX XXXXXXXX TMRLR
XXXXXXXX XXXXXXXX ----0000 0 0 0 0 0 0 0 0 XXXXXXXX XXXXXXXX ----0000 0 0 0 0 0 0 0 0
Reload Timer 3
XXXXXXXX XXXXXXXX
Reload Timer 4
Reserved (R/W)
DPDP --------------DACSR 00000000 00000000 DATCR XXXXXXXX XXXX0 0 0 0
-------(R/W)
-0 0 0 0 0 0 0
00000000 00000000 (R/W) XXXX0 0 0 0 XXXX0 0 0 0
DMAC
BSD0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (R/W) (R/W) (R/W) ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 XXXXXXXX BSD1 XXXXXXXX BSDC XXXXXXXX BSRR XXXXXXXX (R/W) (R/W) (R/W) ICR01 ICR05 ICR09 (W) XXXXXXXX XXXXXXXX (R/W) XXXXXXXX XXXXXXXX (W) XXXXXXXX XXXXXXXX (R) XXXXXXXX XXXXXXXX ICR02 ICR06 ICR10 (R/W) (R/W) (R/W) ICR03 ICR07 ICR11 (R/W) (R/W) (R/W) ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 Interrupt Control Unit Bit Search Module
Reserved
----1 1 1 1 ----1 1 1 1 ----1 1 1 1
(Continued)
32
MB91133/MB91F133
Address 00040CH 000410H 000414H 000418H 00041CH 000420H 000424H 000428H 00042CH 000430H 000434H to 00047CH 000480H 000484H 000488H 00048CH to 0005FCH ICR12 ICR16 ICR20 ICR24 ICR28 ICR32 ICR36 ICR40 ICR44 DICR
Register +0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ICR13 ICR17 ICR21 ICR25 ICR29 ICR33 ICR37 ICR41 ICR45 HRCL ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 -------0 +1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ICR14 ICR18 ICR22 ICR26 ICR30 ICR34 ICR38 ICR42 ICR46 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ---1 1 1 1 1
RSRR/WTCR (R/W)
+2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ICR15 ICR19 ICR23 ICR27 ICR31 ICR35 ICR39 ICR43 ICR47 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1
+3 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1 ----1 1 1 1
Block
Interrupt Control Unit
Delay Int
Reserved PDRR (R/W) CTBR (W) Clock Control Unit
STCR WPR
(R/W) (W)
1 XXXX - 0 0 GCR CT (R/W) (R/W) 1 1 0 0 1 1-1 0 0--0-0 0
0 0 0 1 1 1-XXXXXXXX
----0 0 0 0
XXXXXXXX
PLL Control
Reserved
(Continued)
33
MB91133/MB91F133
Address 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH 000630H 000634H to 0007BCH 0007C0H 0007C4H 0007C8H to 0007F8H FLCR FWTC DDR3
Register +0 (W) DDR2 DDR6 00000000 ASR1 ASR2 ASR3 ASR4 ASR5 AMD0 AMD5 (R/W) (R/W) (W) AMD1 +1 (W) (W) DDR5 00000000 00000000 (W) (W) (W) (W) (W) (R/W) +2 (W) DDR4 DDR8 (W) (W) (W) (W) (W) AMD4 (R/W) +3 (W) (W)
Block
00000000 AMR1 AMR2 AMR3 AMR4 AMR5 AMD32 (R/W)
00000000 -0 0 0 0 0 0 0
Data Direction Register
00000000 00000001 00000000 00000010 00000000 00000011 00000000 00000100 00000000 00000101 ---0 0 1 1 1 0--0 0 0 0 0 EPCR0 ----1 1 0 0 -1----- PCR6 (R/W) 0--0 0 0 0 0
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 EPCR1 (W) 0--0 0 0 0 0 T-unit
-------- 1 1 1 1 1 1 1 1
00000000 (R/W) (R/W)
Pull-up Control
Reserved
000X0000 -----0 0 0
FLASH Control
Reserved
(Continued)
34
MB91133/MB91F133
(Continued)
Address Register +0 +1 LER +2 (W) MODR +3 (W) Block Little Endian Register Mode Register
0007FCH
-----0 0 0
XXXXXXXX
*1 : Do not execute RMW instructions to registers with write-only bits. *2 : Do not execute write access to read-only or reserved registers except for particular requests. *3 : Data in areas with "-" or reserved ones are unspecified. *4 : RMW instructions (RMW : Read / Modify / Write) AND Rj, @Ri OR Rj, @Ri ANDH Rj, @Ri ORH Rj, @Ri ANDB Rj, @Ri ORB Rj, @Ri BANDL #u4, @Ri BORL #u4, @Ri BANDH #u4, @Ri BORH #u4, @Ri EOR EORH EORB BEORL BEORH Rj, @Ri Rj, @Ri Rj, @Ri #u4, @Ri #u4, @Ri
35
MB91133/MB91F133
s INTERRUPTION VECTOR
Causes of MB91130 interruptions and allocation of interruption vectors and interruption control registers are described in the interruption vector table. Interruption number Interruption Address *2 Interruption sauce Offset of TBR default level *1 Decimal Hexadecimal Reset System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation System reservation Exceptions to undefined instructions System reservation External interruption 0 External interruption 1 External interruption 2 External interruption 3 External interruption 4 External interruption 5 External interruption 6 External interruption 7 External interruption 8 to 15 External interruption 16 to 23 UART0 (Reception completion) UART1 (Reception completion) UART2 (Reception completion) UART3 (Reception completion) UART4 (Reception completion) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H
(Continued)
36
MB91133/MB91F133
Interruption sauce UART0 (Transmission completion) UART1 (Transmission completion) UART2 (Transmission completion) UART3 (Transmission completion) UART4 (Transmission completion) DMAC (end, error) Reload timer 0 Reload timer 1 Reload timer 2 Reload timer 3 Reload timer 4 A/D (sequential type) PPG0 PPG1 PPG2 PPG3 PPG4/5 Waveform generator U/D counter 0 (compare/ underflow-overflow, up/down invert) U/D counter 1 (compare/ underflow-overflow, up/down invert) ICU0 (load) ICU1 (load) ICU2 (load) ICU3 (load) OCU0 (matched) OCU1 (matched) OCU2 (matched) OCU3 (matched) OCU4/5 (matched) OCU6/7 (matched) Level comparator 16-bit freerun timer Delay interruption factor bit
Interruption level *1 Decimal Hexadecimal 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Interruption number
Offset 380H 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H
Address *2 of TBR default 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H
(Continued)
37
MB91133/MB91F133
(Continued)
Interruption sauce System reservation (used under REALOS *3) System reservation (used under REALOS *3) Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Used under INT instruction Interruption level *1 Decimal Hexadecimal 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interruption number Offset 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H Address *2 of TBR default 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H
*1 : ICR sets the interruption level for each interruption request using the register built into the interruption controller. ICR is prepared in accordance with each interruption request. *2 : TBR is the register that indicates the starting address of the vector table for EIT. Addresses with added offset values that are specified per TBR and EIT factor will be the vector addresses. *3 : 0X40, 0X41 interruptions for system codes are used in the event that REALOS/FR is used.
38
MB91133/MB91F133
s PERIPHERAL RESOURCES
1. Bus Interface
The bus interface controls the interface with external memory and external I/O. * * * * * * * Bus Interface Characteristics 24-bit (16 MB) address output 16/8-bit bus width can be set. Insertion of programmable "automatic memory wait" (maximum of 7 cycles) Supports "little endian" mode Unused addresses / data pins can be used as I/O ports. Clock doubled should be used if the external bus exceeds 25 MHz. Bus speed is 1/2 of the CPU speed.
* Areas A total of six types of chip selection areas are prepared for the bus interface. The position of each area can be randomly arranged per 64 KB at least using area selection registers (ASR1 to ASR 5) and area mask registers (AMR1 to AMR 5) in an area of 4 GB. The area 0 is allocated to space outside the area specified by ASR1 to ASR5. External areas other than 00010000H to 0005FFFFH are deemed area 0 on resetting. There is no chip selection output pin so no setting is required. Setting it has no effect on usage. Figure 4.1-1 shows an example in which areas 1 to 5 are arranged from 00100000H to 0014FFFFH in 64 KB units. Also, Figure 4.1-2 shows an example in which area 1 is arranged as 00000000H to 0007FFFFH in 512 KB and areas 2 to 5 are arranged as 00100000H to 004FFFFFH in 1-MB units.
00000000H 00000000H 00080000H 00080000H CS0 (1 Mbyte) 000FFFFFH CS2 (1 Mbyte) 000FFFFFH 0010FFFFH 0011FFFFH 0012FFFFH 0013FFFFH 0014FFFFH CS1 (64 Kbyte) CS2 (64 Kbyte) CS3 (64 Kbyte) CS4 (64 Kbyte) CS5 (64 Kbyte) 004FFFFFH 003FFFFFH CS5 (1 Mbyte) 002FFFFFH CS4 (1 Mbyte) 001FFFFFH CS3 (1 Mbyte) CS1 (512 K) CS0 (512 K)
CS0
CS0
Figure 4.1-1 Area Arrangement Example 1
Figure 4.1-2 Area Arrangement Example 2
39
MB91133/MB91F133
* Block Diagram
ADDRESS BUS
A - Out DATA BUS M U X External DATA Bus
write buffer
switch
read buffer
switch DATA BLOCK ADDRESS BLOCK +1 or +2
address buffer inpage
shifter
External Address Bus
CS0 - CS5 ASR AMR comparator
External pin control area Controls all blocks registers & Control
RD WR0. WR1 BRQ BGRNT RDY
40
MB91133/MB91F133
* Register List
Address 0000060CH 0000060EH 00000610H 00000612H 00000614H 00000616H 00000618H 0000061AH 0000061CH 0000061EH 00000620H 00000622H 00000624H 00000626H
AMD0 AMD32 AMD5 RFCR 15 87 ASR1 AMR1 ASR2 AMR2 ASR3 AMR3 ASR4 AMR4 ASR5 AMR5 AMD1 AMD4 0
Area Select Register 1 Area Mask Register 1 Area Select Register 2 Area Mask Register 2 Area Select Register 3 Area Mask Register 3 Area Select Register 4 Area Mask Register 4 Area Select Register 5 Area Mask Register 5 Area Mode Register 0 / Area Mode Register 1 Area Mode Register 32 / Area Mode Register 4 Area Mode Register 5 ReFresh Control Register
0000062CH 0000062EH
DMCR4 DMCR5
DRAM Control Register 4 DRAM Control Register 4
00000688H
EPCR0
EPCR1
External Pin Control Register
000007FEH
LER
MODR
Little Endian Register / MODe Register
Note : Functional pins have not been prepared in the shaded area for MB91133/MB91F133, so these registers should not be accessed.
41
MB91133/MB91F133
2. I/O Port
MB91133/MB91F133 can be used as an I/O port when the setting for resources dealing with each pin does not use the pin for input/output. As regards the read value of the port (PDR) , the pin level is read out when input is set for the port. If output is set, the data register value is read out. This is the same for reading under Read Modify Write. If the input setting is changed to output setting, output data should be set first. If Read Modify Write instructions (i.e. bit set) are used in this case, the data that is read out is the input data from the pin and is not the latch value of the data register, so care must be taken. * Basic I/O Port Block Diagram
Data bus 0 Resource input
1 PDR read 0 PDR Resource output Resource output permission pin
1
DDR
PDR : Port Data Register DDR : Data Direction Register
* I/O Port Register The I/O port consists of the Port Data Register (PDR) and Port Direction Register (DDR) . * In case of input mode (DDR = "0") When PDR reads : Level of external pins handled is read out. When PDR writes : Set value is written in PDR. * In case of output mode (DDR = "1") When PDR reads : PDR values are read out. When PDR writes : PDR values are output to the external pin handled. * Switching control for resources and ports of the analog pin (A/D) * Resources and ports of the analog pin (A/D) are switched using the Analog Input Control register on Port K (AICK) . This controls whether Port K is used as an analog or general-purpose port. 0 : General-purpose port 1 : Analog input (A/D)
42
MB91133/MB91F133
* Block Diagram of Input/Output Port (with Pull-up Resistance)
Data bus 0 Resource input
1 PDR read 0 PDR Resource output Resource output permission
Pull up resistance
(approximately 50 k) pin
1
DDR
PCR PDR : Port Data Register DDR : Data Direction Register PCR : Pull-up Control Register
* Pull-up resistance control register (PCR) R/W Turns pull-up resistance ON/OFF. 0 : Pull-up resistance turned off 1 : Pull-up resistance turned on Notes : * The pull-up resistance control register setting is handled as a priority in stop mode (HIZ = 1) as well. * Use of the pull-up resistance control function is prohibited when the pin concerned is used as the external bus pin. "1" should not be written in this register.
43
MB91133/MB91F133
* Block Diagram of Input / Output Port (Open-drain Output Function with Pull-up Resistance)
Data bus 0 Resource input
1 PDR read 0 PDR Resource output Resource output permission DDR pin
1
ODCR
PCR PDR : Port Data Register DDR : Data Direction Register ODCR : OpenDrain Control Register PCR : Pull-up Control Register
* Pull-up resistance control register (PCR) R/W Controls pull up resistance ON/OFF. 0 : Without pull-up resistance 1 : With pull-up resistance * Open-drain control register (ODCR) R/W Controls open-drain in output mode. 0 : Standard output port in output mode 1 : Open-drain output port in output mode Notes : * This has no meaning in input mode (output Hi-Z) . Input/output mode is decided by the Direction Register (DDR) . * Pull-up resistance control register setting is handled as the priority in stop mode (HIZ = 1) as well. * Use of both the pull-up resistance control function and open-drain control function are prohibited when the pin concerned is used as an external bus pin. "1" should not be written in both registers.
44
MB91133/MB91F133
* Port Data Register (PDR) PDR2 Address : 000001H PDR3 Address : 000000H PDR4 Address : 000007H PDR5 Address : 000006H PDR6 Address : 000005H PDR8 Address : 00000BH PDRC Address : 000013H PDRD Address : 000012H PDRE Address : 000011H PDRF Address : 000010H PDRG Address : 000017H PDRH Address : 000016H PDRI Address : 000015H PDRJ Address : 000014H PDRK Address : 00001BH PDRL Address : 00001AH
7 P27 7 P37 7 P47 7 P57 7 P67 7 7 PC7 7 PD7 7 PE7 7 PF7 7 7 7 7 7 PK7 7 PL7 6 P26 6 P36 6 P46 6 P56 6 P66 6 P86 6 PC6 6 PD6 6 PE6 6 PF6 6 6 6 6 6 PK6 6 PL6 5 P25 5 P35 5 P45 5 P55 5 P65 5 P85 5 PC5 5 PD5 5 PE5 5 PF5 5 PG5 5 5 PI5 5 PJ5 5 PK5 5 PL5 4 P24 4 P34 4 P44 4 P54 4 P64 4 P84 4 PC4 4 PD4 4 PE4 4 PF4 4 PG4 4 4 PI4 4 PJ4 4 PK4 4 PL4 3 P23 3 P33 3 P43 3 P53 3 P63 3 P83 3 PC3 3 PD3 3 PE3 3 PF3 3 PG3 3 3 PI3 3 PJ3 3 PK3 3 PL3 2 P22 2 P32 2 P42 2 P52 2 P62 2 P82 2 PC2 2 PD2 2 PE2 2 PF2 2 PG2 2 PH2 2 PI2 2 PJ2 2 PK2 2 PL2 1 P21 1 P31 1 P41 1 P51 1 P61 1 P81 1 PC1 1 PD1 1 PE1 1 PF1 1 PG1 1 PH1 1 PI1 1 PJ1 1 PK1 1 PL1 0 P20 0 P30 0 P40 0 P50 0 P60 0 P80 0 PC0 0 PD0 0 PE0 0 PF0 0 PG0 0 PH0 0 PI0 0 PJ0 0 PK0 0 PL0
Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - XXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - - XXXXXXB Initial value - - - - - XXXB Initial value - - XXXXXXB Initial value - - XXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB
Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W Access R/W
PDR2 to L are input/output data registers of the I/O port. Input/output control is carried out by DDR2 to L that are handled. 45
MB91133/MB91F133
* Data Direction Register (DDR) DDR2 Address : 000601H DDR3 Address : 000600H DDR4 Address : 000607H DDR5 Address : 000606H DDR6 Address : 000605H DDR8 Address : 00060BH DDRC Address : 0000D3H DDRD Address : 0000D2H DDRE Address : 0000D1H DDRF Address : 0000D0H DDRG Address : 0000D7H DDRH Address : 0000D6H DDRI Address : 0000D5H DDRJ Address : 0000D4H DDRK Address : 0000DBH DDRL Address : 0000DAH
7 P27 7 P37 7 P47 7 P57 7 P67 7 7 PC7 7 PD7 7 PE7 7 PF7 7 7 7 7 7 PK7 7 PL7 6 P26 6 P36 6 P46 6 P56 6 P66 6 P86 6 PC6 6 PD6 6 PE6 6 PF6 6 6 6 6 6 PK6 6 PL6 5 P25 5 P35 5 P45 5 P55 5 P65 5 P85 5 PC5 5 PD5 5 PE5 5 PF5 5 PG5 5 5 PI5 5 PJ5 5 PK5 5 PL5 4 P24 4 P34 4 P44 4 P54 4 P64 4 P84 4 PC4 4 PD4 4 PE4 4 PF4 4 PG4 4 4 PI4 4 PJ4 4 PK4 4 PL4 3 P23 3 P33 3 P43 3 P53 3 P63 3 P83 3 PC3 3 PD3 3 PE3 3 PF3 3 PG3 3 3 PI3 3 PJ3 3 PK3 3 PL3 2 P22 2 P32 2 P42 2 P52 2 P62 2 P82 2 PC2 2 PD2 2 PE2 2 PF2 2 PG2 2 PH2 2 PI2 2 PJ2 2 PK2 2 PL2 1 P21 1 P31 1 P41 1 P51 1 P61 1 P81 1 PC1 1 PD1 1 PE1 1 PF1 1 PG1 1 PH1 1 PI1 1 PJ1 1 PK1 1 PL1 0 P20 0 P30 0 P40 0 P50 0 P60 0 P80 0 PC0 0 PD0 0 PE0 0 PF0 0 PG0 0 PH0 0 PI0 0 PJ0 0 PK0 0 PL0
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access - 0000000B W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access - - 000000B R/W
Initial value Access - - - - - 000B R/W
Initial value Access - - 000000B R/W
Initial value Access - - 000000B R/W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
DDR0 to L control input/output direction of the I/O ports handled per bit. DDR = 0 : Port input DDR = 1 : Port output "0" must be written into the empty bit. 46
MB91133/MB91F133
* Pull up Control Register (PCR) PCR6 Address : 000631H PCRC Address : 0000C3H PCRD Address : 0000C2H PCRE Address : 0000C1H PCRH Address : 0000C6H PCRI Address : 0000C5H PCRJ Address : 0000C4H
7 P67 7 PC7 7 PD7 7 7 7 7 6 P66 6 PC6 6 PD6 6 6 6 6 5 P65 5 PC5 5 PD5 5 5 5 PI5 5 PJ5 4 P64 4 PC4 4 PD4 4 4 4 PI4 4 PJ4 3 P63 3 PC3 3 PD3 3 3 3 PI3 3 PJ3 2 P62 2 PC2 2 PD2 2 2 PH2 2 PI2 2 PJ2 1 P61 1 PC1 1 PD1 1 PE1 1 PH1 1 PI1 1 PJ1 0 P60 0 PC0 0 PD0 0 PE0 0 PH0 0 PI0 0 PJ0
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access - - - - - - 00B R/W
Initial value Access - - - - - 000B R/W
Initial value Access - - 000000B R/W
Initial value Access - - 000000B R/W
PCR6 to J carry out pull-up resistance control of the I/O ports handled. PCR = 0 : Pull-up resistance turned off PCR = 1 : Pull-up resistance turned on
* Open-drain Control Register (ODCR) OCRH Address : 0000CAH OCRI Address : 0000C9H OCRJ Address : 0000C8H
7 7 7 6 6 6 5 5 PI5 5 PJ5 4 4 PI4 4 PJ4 3 3 PI3 3 PJ3 2 PH2 2 PI2 2 PJ2 1 PH1 1 PI1 1 PJ1 0 PH0 0 PI0 0 PJ0
Initial value Access - - - - - 000B R/W
Initial value Access - - 000000B R/W
Initial value Access - - 000000B R/W
OCRH to J carry out open-drain control in output mode of the I/O ports handled. OCR = 0 : Standard output port in output mode OCR = 1 : Open-drain output port in output mode This has no meaning in input mode (output Hi-z) .
47
MB91133/MB91F133
* Analog Input Control Register (AICR) AICK Address : 0000CFH
7 PK7 6 PK6 5 PK5 4 PK4 3 PK3 2 PK2 1 PK1 0 PK0
Initial value Access 00000000B R/W
AICK controls each pin of the I/O ports handled as follows. AIC = 0 : Analog input mode AIC = 1 : Port input mode Set to "0" when reset.
48
MB91133/MB91F133
3. 8/16-bit Up/Down Counter / Timer
8/16-bit up/down counter / timer is configured of event input pins x 6, 8-bit up/down counters x 2, 8-bit reload / compare registers x 2 and their control circuits. * Characteristics of 8/16-bit Up/Down Counter / Timer * Counting from (0) d to (256) d is possible using an 8-bit counting register. (Counting from (0) d to (65535) d is possible in 16-bit x 1 operation mode.) * 4 types of counting mode can be selected by the count clock * Selection can be made from two types of internal clock as the count clock in timer mode. * Detection edge of the external pin input signals can be selected in up/down count mode. * Phase difference count mode is suited to count encoders such as motors. Turning angle and turning number, etc., can easily and accurately be counted by separately inputting phase A, B and Z outputs of the encoder. * Selection can be made from two function types for the ZIN pin (valid for all modes) . * Compare and reload functions are featured, and each function can be used alone or in combination. Up/down counting with random width can be carried out using both functions in combination. * The count direction directly before can be identified by the count direction flag. * Generation of interruptions in case of compared match, reload (underflow) or overflow and in cases where the count direction is changed can be controlled separately.
49
MB91133/MB91F133
* Block Diagram 8/16-bit Up/Down Counter / Timer (ch0)
Data bus 8 bit CGE1 CGE0 C/GS ZIN0 Reload / Compare Register 0 (RCR0) RCUT Reload control
Edge/level detection
UCRE
RLDE
UDCC
Counter clear 8 bit Up/Down Count Register 0 (UDCR0) Carry
CES1 CES0 CMS1 CMS0 CITE AIN0 BIN0 Up/down count clock selection Count clock UDF1 UDF0 CDCF CFIE Interruption output UDFF OVFF UDIE
CMPF
Pre-scalar
CSTR
CLKS
50
MB91133/MB91F133
8/16-bit Up/Down Counter / Timer (ch1)
Data bus 8 bit CGE1 CGE0 C/GS ZIN1 Reload / Compare Register 1 (RCR1) RCUT Reload control
Edge/level detection
UCRE
RLDE
UDCC
Counter clear 8 bit Up/Down Count Register 1 (UDCR1) CMPF UDFF OVFF
CMS1 CMS0 CES1 CES0 M16E Carry Count clock AIN1 BIN1 Up/down count clock selection UDF1 UDF0 CDCF CFIE Interruption output CITE UDIE
Pre-scalar
CSTR
CLKS
51
MB91133/MB91F133
* Register List
31 RCR1 CCRH0 CCRH1 24 23 RCR0 CCRL0 CCRL1 16 15 UDCR1 87 UDCR0 CSR0 CSR1 0
Up/down count register ch0 (UDCR0) bit 7 6 Address : 000087H D07 D06 Up/down count register ch1 (UDCR1) bit 15 14 Address : 000086H D17 D16 Reload compare register ch0 (RCR0) bit 7 6 Address : 000085H
D07 D06
5 D05
4 D04
3 D03
2 D02
1 D01
0 D00
13 D15
12 D14
11 D13
10 D12
9 D11
8 D10
5 D05
4 D04
3 D03
2 D02
1 D01
0 D00
Reload compare register ch1 (RCR1) bit 15 14 Address : 000084H D17 D16 Counter Status register ch0, 1 (CSR0, 1) bit 7 6 00008BH Address : CSTR CITE 00008FH
13 D15
12 D14
11 D13
10 D12
9 D11
8 D10
5 UDIE
4 CMPF
3 OVFF
2 UDFF
1 UDF1
0 UDF0
Counter control register ch0, 1 (CCRL0, 1) bit 7 6 5 000089H Address : CTUT UCRE 00008DH Counter control register ch0 (CCRH0) bit 15 14 Address : 000088H M16E CDCF Counter control register ch1 (CCRH1) bit 15 14 Address :00008CH CDCF
4 RLDE
3 UDCC
2 CGSC
1 CGE1
0 CGE0
13 CFIE
12 CLKS
11 CMS1
10 CMS0
9 CES1
8 CES0
13 CFIE
12 CLKS
11 CMS1
10 CMS0
9 CES1
8 CES0
52
MB91133/MB91F133
4. 16-bit Reload Timer
The 16-bit timer is configured with a 16-bit down counter, 16-bit reload register, pre-scalar to prepare the internal count clock and control register. Selection can be made from three types of internal clocks (machine clock 2 / 8 / 32 cycles) as the input clock. DMA transfer can be initiated by interruption. The MB91133/MB91F133 features a 5-channel timer. * Block Diagram
16 16-bit reload register 8 Reload RELD 16 16-bit down counter 2 R - BUS GATE CSL1 Clock selector CSL0 2 IN CTL. EXCK Pre-scalar clear 3 MOD2 MOD1 MOD0 3 PWM (ch0, ch1) A/D (ch2) Re-trigger TRG CNTE OUT CTL. 2 UF OUTE OUTL INTE UF IRQ
21 23 25
Channel 2TO output of the reload timer is connected to the A/D converter inside the LSI. Thus, A/D conversion can be started up at the cycle set in the reload register.
53
MB91133/MB91F133
5. PPG Timer
The PPG timer can efficiently output accurate PWM waveforms. The MB91130 series features a 6-channel PPG timer. * PPG Timer Characteristics * Each channel is configured with a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare register with duty setting buffer and pin control area. * Selection can be made from four types of count clocks for 16-bit down counters. Internal clock , 4, 16, 64 * Counter values can be initialized to "FFFFH" by resetting and counter borrowing. * PWM output is available per channel. * Register outline Cycle setting register : Reloading register with buffer Duty setting register : Compare register with buffer Transfer from buffer is carried out by counter borrowing. * Pin control outline Set to "1" by duty match. (Priority) Resets to "0" by counter borrowing. All "L" (or "H") can simply be output by using the output values fixing mode. Polarization can also be specified. * Interruption request can be generated by selecting from the following combinations. Initiation of this timer Counter borrow generation (cycle match) Duty match generation Counter borrow generation (cycle match) or duty match generation DMA transfer can be initiated by the above interruption requests. * Simultaneous initiation of a number of channels can be set by software or other interval timers. Re-start during operation can also be set.
54
MB91133/MB91F133
* Block Diagram Overall Block Diagram of PPG Time
16-bit reload timer ch0 TRG input PWM timer ch0
PWM0
16-bit reload timer ch1 General control register 1 (factor selection) General control register 2 4
TRG input PWM timer ch1
PWM1
TRG input PWM timer ch2
PWM2
4 External TRG0 to 3 External TRG4
TRG input PWM timer ch3
PWM3
PWM timer ch4
PWM4
External TRG5
PWM timer ch5
PWM5
55
MB91133/MB91F133
Block Diagram of PPG Timer for 1 Channel
PCSR PDUT
Pre-scalar 1/1 1/4 1 / 16 1 / 64
CK 16-bit down counter Start
Load
CMP
Borrow
PPG mask S Peripheral system clock Q
PWM OUTPUT
R
Reverse bit Enable TRG input Edge detection Soft trigger Interruption selection IRQ
56
MB91133/MB91F133
* Register list
Address 000000DCH 000000DFH 15
GCN1
0 R/W
GCN2
General control register 1 General control register 2
R/W
000000E0H 000000E2H 000000E4H 000000E6H
PCNH
PTMR PCSR PDUT PCNL
R W W R/W
ch0 Timer register ch0 Peripheral setting register ch0 Duty setting register ch0 Control status register
000000E8H 000000EAH 000000ECH 000000EEH
PCNH
PTMR PCSR PDUT PCNL
R W W R/W
ch1 Timer register ch1 Peripheral setting register ch1 Duty setting register ch1 Control status register
000000F0H 000000F2H 000000F4H 000000F6H
PCNH
PTMR PCSR PDUT PCNL
R W W R/W
ch2 Timer register ch2 Peripheral setting register ch2 Duty setting register ch2 Control status register
000000F8H 000000FAH 000000FCH 000000FEH
PCNH
PTMR PCSR PDUT PCNL
R W W R/W
ch3 Timer register ch3 Peripheral setting register ch3 Duty setting register ch3 Control status register
(Continued)
57
MB91133/MB91F133
(Continued)
Address 00000100H 00000102H 00000104H 00000106H
15
PTMR PCSR PDUT PCNH PCNL
0 R W W R/W ch4 Timer register ch4 Peripheral setting register ch4 Duty setting register ch4 Control status register
00000108H 0000010AH 0000010CH 0000010EH
PCNH
PTMR PCSR PDUT PCNL
R W W R/W
ch5 Timer register ch5 Peripheral setting register ch5 Duty setting register ch5 Control status register
58
MB91133/MB91F133
6. Multifunction Timer
The multifunction timer unit is configured of a 16-bit freerun timer x 1, 16-bit output compare x 8, 16-bit input capture x 4, 16-bit PPG timer x 6 ch and waveform generation area modules. 12 independent waveform outputs based on a 16-bit free-run timer are possible using this function and measurement of input pulse width and external clock cycle is also possible. * Multifunction Timer Configuration * 16-bit free-run timer ( x 1) The 16-bit free-run timer consists of a 16-bit up counter, control register, 16-bit compare clear register and pre-scalar. Output values of this counter are used as the base timer for output compare and input capture. * Counter operation clocks can be selected from six types. Six types of internal clocks (2, 4, 8, 16, 32, 64) : Machine clock * Interruption can be generated by overflow of the counter value and a compared match with compare clear register. (Mode setting is required for a compared match.) * Counter value can be initialized to "0000H" by a compared match with the reset, software clear or the compare clear register. * Output compare ( x 8) Output compare is configured of 16-bit compare register x 8, latch for compare output and control register. Interruption can be generated as well as reversing output level when the 16-bit free-run timer value and compare register value match. * 8 compare registers can be operated independently. Output pins and interruption flags support each compare register. * Output pins can be controlled by pairing two compare registers. Output pins are reversed using two compare registers. * Initial value of each output pin can be set. * Interruption can be generated by matching compare. * Input capture ( x 4) Input capture is configured with four independent external input pins , supported capture and control register. 16-bit free-run timer value is held in the capture register by detecting the random edge of signals that are input by the external input pin, and interruption can simultaneously be generated. * Valid edges (rising edge, falling edge, both edges) of external input signals can be selected. * Four input captures can be operated independently. * Interruption can be generated by the valid edges of external input signals. * 16-bit PPG timer ( x 6) Refer to PPG timer
59
MB91133/MB91F133
* Waveform Generation Area The waveform generation area is configured with 8-bit timer x 3, 8-bit reload register x 3, timer control register x 3 and 8-bit waveform control register. This control circuit controls the waveform of the 16-bit PPG timer and real-time output, and DC chopper output and non-overlapping 3-phase waveform output to be used for inverter control are possible. * Non-overlapping pulse output of the PPG timer is possible by setting dead time of the 8-bit timer (dead time timer function) . * Real timer output is operated by the 2-channel mode and non-overlapping output of the waveform is possible by setting the dead time of the 8-bit timer (dead time timer function) . * Operation of PPG timer can easily be started/stopped by generating a GATE signal for the PPG timer operation through match detection of real-time output compare (GATE function). * The 8-bit timer is operated by match detection of real-time output compare, and operation of the PPG timer can easily be started/stopped by generating a GATE signal for the PPG timer until the 8-bit timer is stopped (GATE function) . * Pin output can be forcibly controlled by input to the DTTI pin. Pins can be controlled externally even if oscillations stop due to lack of clocks for inputs to this pin. (Each pin level can be set by the program .) If this function is used, the port should be set to output (DDR = 1) and the output value should be described in the PDR beforehand.
60
MB91133/MB91F133
* Block Diagram Block Diagram of PPG Timer for 1 Channel
Interruption IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Cycle device Clock
16-bit free-run timer
16-bit compare clear register (Ch. 6 compare register) Compare register 0/2/4
Compare circuit MS13 0 T CMOD T Q ICLR Q ICRE
Interruption
Compare circuit Compare register 1/3/5 R-BUS
RT0/2/4 To waveform generation area
Compare circuit
RT1/3/5 To waveform generation area
IOP1
IOP0
IOE1
IOE0 Interruption Interruption
Capture data register 0/2
Edge detection
IN 0/2
EG11
EG10
EG01
EG00
Capture data register 1/3
Edge detection
IN 1/3
ICP0
ICP1
ICE0
ICE1 Interruption Interruption
61
MB91133/MB91F133
Block Diagram of Waveform Generation Area
DCK2 DCK1 DCK0 TMD1 TMD0 NRSL DTIL DTIE
DTTI control circuit Cycle device Clock RT0 RT1 8-bit timer Compare circuit Selector Dead time generation U X Selector Waveform generation area GATE 0/1 TO0 TO1
DTTI
RTO0/U RTO1/X
8-bit timer register 0 R-BUS
GATE 2/3 RT2 RT3 8-bit timer Compare circuit Selector Dead time generation V Y GATE 4/5 RT4 RT5 8-bit timer Compare circuit Selector Dead time generation W Z Selector RTO4/W RTO5/Z Waveform generation area TO4 TO5 Selector RTO2/V RTO3/Y Waveform generation area TO2 TO3
8-bit timer register 1
8-bit timer register 2
62
MB91133/MB91F133
* Registers List
Address
15
87 IPCP ICS OCCP OCS TCDT TCCS DTCR TMRR STGCR
0
000044H to 4BH 00004DH, 4FH 000054H to 63H 000064H to 6BH 00006CH, 6DH 00006EH, 6FH 0000ACH, AEH B2H 0000ADH, AFH B3H 0000B1H
(R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
63
MB91133/MB91F133
7. External Interruption
The external interruption control area is the block that controls the external interruption requests input in INT0 to INT23. The level of request to be detected can be selected from "H", "L", "Rising edge" or " Falling edge". * Block diagram
R-BUS 24
Interruption permission register
Interruption requests
24 Gate Factor F/F Edge detection circuit
24
INT0 to INT23
24
Interruption factor register
48 Request level setting register
* Register List External interruption permission register (ENIR) 15 14 13 bit
ER7 ER6 ER5
12 ER4
11 ER3
10 ER2
9 ER1
8 ER0
External interruption factor register (EIRR) 15 14 13 bit
ER7 ER6 ER5
12 ER4
11 ER3
10 ER2
9 ER1
8 ER0
Request level setting register (ELVR) 7 6 bit
LB3 LA3 14 LA7
5 LB2 13 LB6
4 LA2 12 LA6
3 LB1 11 LB5
2 LA1 10 LA5
1 LB0 9 LB4
0 LA0 8 LA4
bit
15 LB7
There are three sets of the above registers (for 8 channels) for a total of 24 channels.
64
MB91133/MB91F133
8. Delay Interruption Module
The delay interruption module generates interruptions for task switching. Interruption requests to the CPU can be generated / cancelled using software with this module. * Block Diagram Refer to "9.(2) Block Diagram of Interruption Controller" for the block diagram of the delay interruption generation area. * Register List
bit 7 6 5 4 3 2 1 0 DLYI R/W
Address : 00000430H
DICR
65
MB91133/MB91F133
9. Interruption Controller
The interruption controller carries out interruption reception and arbitration. * Hardware configuration of the interruption controller This module consists of the following items. * ICR register * Interruption priority judgement circuit * Interruption level, interruption number (vector) generation area * Cancellation request generation area for HOLD request * Major interruption controller functions This module has the following functions. * Detection of interruption requests * Priority grade judgement (depending on the level and number) * Transferring interruption level of factors for the judgement results (to CPU) * Transferring interruption number of factors for the judgement results (to CPU) * Recovery instruction from stop mode by generating interruption * Cancellation of HOLD request to the bus master * Resetting Interruption Factors There are restrictions between RETI instructions and those for resetting interruption factors in the interruption routine.
66
MB91133/MB91F133
* Block Diagram
INT0
IM
OR NMI
Priority grade judgement 5 NMI processing 4 LEVEL judgement ICR00 Generation of LEVEL / VECTOR HLDREQ (Holding request)
LEVEL4 to 0
HLDCAN
RI00 VECTOR judgement ICR47 RI47 (DLYIRQ) DLYI
6
VCT5 to 0
R-BUS
Note : DLYI shown in the figure indicates delay interruption area. (Refer to the chapter on the delay interruption module for details.) INTO is the wake-up signal to the clock control area in case of sleep or stop. HLDCAN is the bus vacation request signal to bus masters other than the CPU. There is no NMI function in this model.
67
MB91133/MB91F133
* Register List
bit 7 6 5 4 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 R/W 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 R/W 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 R/W 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 R/W
Address : 00000400H Address : 00000401H Address : 00000402H Address : 00000403H Address : 00000404H Address : 00000405H Address : 00000406H Address : 00000407H Address : 00000408H Address : 00000409H Address : 0000040AH Address : 0000040BH Address : 0000040CH Address : 0000040DH Address : 0000040EH Address : 0000040FH Address : 00000410H Address : 00000411H Address : 00000412H Address : 00000413H Address : 00000414H Address : 00000415H Address : 00000416H Address : 00000417H Address : 00000418H Address : 00000419H Address : 0000041AH Address : 0000041BH Address : 0000041CH Address : 0000041DH Address : 0000041EH Address : 0000041FH

ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31
(Continued)
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MB91133/MB91F133
(Continued)
bit 7 6 5 4 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 R/W 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 R/W 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 R/W 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 R/W
Address : 00000420H Address : 00000421H Address : 00000422H Address : 00000423H Address : 00000424H Address : 00000425H Address : 00000426H Address : 00000427H Address : 00000428H Address : 00000429H Address : 0000042AH Address : 0000042BH Address : 0000042CH Address : 0000042DH Address : 0000042EH Address : 0000042FH

ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Address : 00000431H

LVL3 R/W
LVL2 R/W
LVL1 R/W
LVL0 R/W
HRCL
69
MB91133/MB91F133
10. Clock Generation Area (low power consumption mechanism)
Clock generation area is a module with the following functions. * CPU clock generation (including gear function) * Peripheral clock generation (including gear function) * Reset generation and holding factors * Standby function (including hardware standby) * PLL (Phase Locked Loop) is built in * Register list
Address
7 RSRR/WTCR STCR PDRR CTBR GCR WPR PCTR
0
000480H 000481H 000482H 000483H 000484H 000485H 000488H
Reset factor / watchdog cycle control register Standby control register DMA request blocking register Time base timer clear register Gear control register Watchdog reset generation postponement register PLL / 32-K clock control register
70
MB91133/MB91F133
* Block diagram
[ Gear control area ] GCR register CPU gear Peripheral gear X0A X1A Oscillation circuit 1/2 X0 X1 Oscillation circuit PLL 32-kHz selection circuit [ Stop/sleep control area ] Internal interruption Internal reset STCR register STOP status SLEEP status CPU hold request Reset generation F/F Internal reset M P X Internal clock generation circuit CPU clock Internal bus clock Internal peripheral clock
DMA request PDRR register Status transfer control circuit
Power on detection circuit VCC3 [ Reset factor circuit ]
R GND RST pin [ Watchdog control area ] RSRR register
WPP register Watchdog F/F CTBR register Time base timer Count clock
71
MB91133/MB91F133
11. 8-/10-bit A/D Converter
The 8-/10-bit A/D converter features functions that convert analog input voltages to 10- or 8-bit digital values using the RC sequential comparison conversion method. The input signal is selected from 8-channel analog input pins and three types of conversion initiation can be selected from software, internal clock, or external pin trigger. * characteristics of 8-/10-bit A/D converter The A/D conversion function for converting analog voltages (input voltages) input into the analog input pins to digital values has the following characteristics. * Conversion time is minimum 5.0 s (including sampling time when machine clock is 33 MHz) . * Conversion method is RC sequential comparison conversion method with sample holding circuit. * 10- or 8-bit resolution can be selected. * Analog input pin can be selected from 8 channels using the program. * interruption request can be generated when A/D conversion ends. * Data is not lost even during continuous conversion as conversion data protection function works while interruptions are permitted. * Initiation factors for conversion can be selected from software, 16-bit reload timer 2 (rising edge) , or external pin trigger (L level detection) . There are three types of conversion modes. Table 13.1-1 Conversion Modes of 8-/10-bit A/D Converter Single Conversion Operation Scan Conversion Operation Converts the specified channel (1 channel Converts a series of channels (up to 8 only) once and ends. channels can be specified) once and ends. Repeatedly converts the specified channel Repeatedly converts a series of channels (1 channel only) . (up to 8 channels can be specified) . Suspends after converting the specified channel (1 channel only) once and waits until the next one is initiated. Converts a series of channels (up to 8 channels can be specified) but is suspended between each channel conversion and waits until the next one is initiated.
Conversion Modes Single conversion mode Consecutive conversion mode
Stop conversion mode
72
MB91133/MB91F133
* Block Diagram of 8-/10-bit A/D Converter The 8-/10-bit A/D converter is configured with the following 9 blocks. * A/D control status register (ADCS1, 2) * A/D data register (ADCR) * Clock selector (input clock selector to initiate A/D conversion) * Decoder * Analog channel selector * Sample holding circuit * D/A converter * Comparator * Control circuit * Block Diagram
AVSS AVR MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 D/A converter AVSS
Input circuit Comparator
Sequential comparison register R - BUS Data register Decoder ADCR A/D control register 1 A/D control register 2 16-bit reload timer 2 External pin trigger ADCS1, 2 Operation clock Pre-scalar 8 7 6 5 4 3 2 1
Sample and holding circuit
* Register List
15 14 13 12 11 10 9 0
0000CFH 00003AH 000038H
ADCS1 ADCR
AICK ADCS0
73
MB91133/MB91F133
12. 8-bit D/A Converter
The 8-bit D/A converter is an R-2R type D/A converter with 8-bit resolution. * Characteristics of the 8-bit D/A converter The MB81130 series features a 3-channel D/A converter and output control can be carried out individually by the D/A control register. * Block Diagram of 8-bit D/A Converter The 8-bit D/A converter is configured with the following three blocks. * 8-bit resistance ladder * Data register * Control register * Block Diagram
R - BUS
DA27 to DA20
DA17 to DA10
DA07 to DA00
DAVC DA27 DA17
DAVC DA07
DAVC
DA20
DA10
DA00
DAE Standby control
DAE Standby control
DAE Standby control
DA output
DA output
DA output
74
MB91133/MB91F133
* 8-bit D/A Converter Pins D/A converter pins are dedicated pins. * Registers of 8-bit D/A Converter The 8-bit D/A converter has the following two registers. D/A control register (DACR0, 1, 2) D/A data register (DADR2, 1, 0) * Register list D/A converter data register 0 bit 7 DADR0 DA07 00000ABH D/A converter data register 1 bit 15 DADR1 DA17 00000AAH D/A converter data register 2 bit 23 DADR2 DA27 00000A9H D/A control register 0 bit DACR0 00000A7H D/A control register 1 bit DACR1 00000A6H D/A control register 2 bit DACR2 00000A5H
23 22 21 20 19 18 17 16 DAE2 15 14 13 12 11 10 9 8 DAE1 7 6 5 4 3 2 1 0 DAE0
6 DA06
5 DA05
4 DA04
3 DA03
2 DA02
1 DA01
0 DA00
14 DA16
13 DA15
12 DA14
11 DA13
10 DA12
9 DA11
8 DA10
22 DA26
21 DA25
20 DA24
19 DA23
18 DA22
17 DA21
16 DA20
75
MB91133/MB91F133
13. 4-bit Level Comparator
The 4-bit level comparator is the module that compares input levels (large/small) and compares the size of the analog input voltage with 4-bit digital values. * Functions of the 4-bit level comparator Compares analog voltage that has been input to the analog input pins (input voltage) with 4-bit digital value and has the following characteristics. * Conversion time is minimum 1 s (including sampling time) . * Sampling time is minimum 0.5 s. * Interruption requests can be generated when analog comparison ends. * Interruption of 4-bit level comparator Table 15.1-1 Interruption and DMAC of 4-bit level comparator Interruption control register TBR default Offset address Register name Address ICR45 00042DH 308H 000FFF08H
Interruption number #61 (3DH)
DMAC x
x : Initiation is impossible
76
MB91133/MB91F133
* Block Diagram of 4-bit Level Comparator The 4-bit level comparator is configured with the following three blocks. * Comparator * 4-bit resistance ladder * Control register * Block diagram
AVCC
AVR
AVSS
4-bit D/A (resistance ladder)
RD3 - 0
FR30 R - BUS
AN7
Comparator
Sample & holding circuit
CPLV
INT
INTE
CPEN
Interruption
Reload timer Operation clock
77
MB91133/MB91F133
* Registers of 4-bit Lev el Comparator * Register list
bit 31
bit 24 bit 23 LVLC
bit 16
0000-0018H
Control register (LVLC) bit 0000018H
31 RD3 R/W (X)
30 RD2 R/W (X)
29 RD1 R/W (X)
28 RD0 R/W (X)
27 CPLV R/W (0)
26 INT R/W (0)
25 INTE R/W (0)
24 CPEN R/W (0)
Attribute Initial value
78
MB91133/MB91F133
14. UART
UART is the general-purpose serial data communications interface to carry out synchronous or asynchronous communication (start-stop synchronization) with external systems. It has a master/slave-type communications function (multiprocessor mode: supporting only master side) as well as normal bi-directional communications function (normal mode). * UART Functions UART is the general-purpose serial data communications interface that sends and receives serial data to/from other CPUs and peripheral equipment, and has functions shown in Table 16.1-1. Table 16.1-1 UART Functions Functions Data buffer Transfer mode Full-duplex double buffer * Clock synchronous (without start-stop bit) * Clock asynchronous (start-stop cycle) * Dedicated baud rate generator is available. Can be selected from 8 types. * External clock input is possible. * Internal clock (Internal clocks that are provided from 16-bit reload timer supporting each channel can be used.) * 7-bit (in case of asynchronous normal mode only) * 8-bit Non Return to Zero (NRZ) method * Framing error * Overrun error * Parity error (impossible in case of multiprocessor mode) * Reception interruption (reception completion, reception error detection) * Transmission interruption (transmission completion) Communication between 1 (master) and n (slaves) is possible (Only supports master side)
Baud rate
Data length Signal method Reception error detection
Interruption request Master/slave-type communications function (Multiprocessor mode)
Note : Start / stop bits are not added by UART and only data is transferred. Table 16.1-2 UART Operations Mode Data length Synchronization method Without parity With parity 7-bit or 8-bit 8 + 1* 8
1
Operations mode 0 1 Normal mode Multiprocessor mode
Stop bit length 1-bit or 2-bit *2 N/A
Asynchronous Asynchronous Synchronous
2 Normal mode : Setting is impossible
*1 : " + 1" is address / data selection bit (A/D) to be used to control communications. *2 : 1-bit only can be detected for stop bit in case of reception.
79
MB91133/MB91F133
* UART Block Diagram UART is configured with the following 11 blocks. * Clock selector * Mode register (SMR0 to 4) * Reception control circuit * Control register (SCR0 to 4) * Transmission control circuit * Status register (SSR0 to 4) * Reception status judgement circuit * Input data register (SIDR0 to 4) * Shift register for reception * Output data register (SODR0 to 4) * Sift register for transmission * Block Diagram
Control bus Reception interruption signals #26 to 30 * Transmission clock Reception interruption signals #31 to 35 * Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter
Dedicated baud rate generator Clock selector Reception clock Pin Reception control circuit
16-bit reload timer
Start bit detection circuit Reception bit counter Reception parity counter
Pin
Pin Reception status judgement circuit Shift register for reception Reception ends Shift register for transmission Transmission starts Reception error Generation signal (to CPU)
SIDR0 4
SODR0 4
Internal data bus
SMR0 to 4 registers
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR0 to 4 registers
PEN P SBL CL A/D REC RXE TXE
SSR0 to 4 registers
PE ORE FRE RDRF TDRE BDS RIE TIE
* : Interruption number
80
MB91133/MB91F133
* Block Diagram of UART Pins
Data bus 0 Resource input
1 PDR read 0 PDR Resource output Resource output permission DDR pin
1
ODCR
PCR PDR : Port Data Register DDR : Data Direction Register ODCR : Open-drain Control Register PCR : Pull-up Control Register
* Register List
Address
bit 15
bit 8
bit 7
bit 0
ch0 : 0000_001EH, ch1 : 0000_0022H, ch2 : 0000_0026H, ch3 : 0000_0072H, ch4 : 0000_0076H, ch0 : 0000_001CH, ch1 : 0000_0020H, ch2 : 0000_0024H, ch3 : 0000_0070H, ch4 : 0000_0074H, ch0 : 0000_007AH ch1 : 0000_0078H ch2 : 0000_007EH ch3 : 0000_007CH ch4 : 0000_0082H
1FH 23H 27H 73H 77H 1DH 21H 25H 71H 75H
Control register (SCR)
Mode register (SMR)
Status register (SSR)
Input/output data register (SIDR/SODR)
Communications pre-scalar control register (CDCR)
Vacant
81
MB91133/MB91F133
15. DMA Controller
The DMA controller is the built-in module of the MB91130 series that carrie out direct memory access (DMA) transfers. * * * * * * * * Characteristics of the DMA Controller 8 channels 3 transfer mode types : single/block transfer, burst transfer, continuous transfer Transfer between overall address areas Maximum 65,536 transfers Interruption function when transfer ends Increase/decrease in transfer addresses can be selected using software 3 external transfer request input/output pins and 3 external transfer end output pins
* Block Diagram
DREQ0 to DREQ2
3
Edge / level detection circuit
3
3 3 Sequencer 8
DACK0 to DACK2 EOP0 to EOP2 Interruption request
Built-in resource transfer request
5
Data buffer
Switcher
DPDP Data bus
DACSR
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
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MB91133/MB91F133
* Register List (In DMAC : DMAC internal registers)
31 0
00000200H 00000204H 00000208H
DPDP DACSR DATCR
(On RAM : DMA descriptors)
bit 31 DPDP + 0H DPDP + 0CH bit 0
DMA ch0 Descriptor DMA ch1 Descriptor
DPDP + 54H
DMA ch7 Descriptor
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MB91133/MB91F133
16. Bit Search Module
The bit search module searches for 0, 1 or change points on data that has been written in the input register, and returns the detected bit position. * Block Diagram
D-BUS Input latch
Address decoder
Detection mode
Changing to 1 detection data
Bit search circuit
Detection results
* Register List
31 0 BSD0 BSD1 BSDC BSRR
Address : 000003F0H Address : 000003F4H Address : 000003F8H Address : 000003FCH
Data register for 0 detection Data register for 1 detection Data register for change point detection Detection results register
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MB91133/MB91F133
17. FLASH Memory
The MB91FV130 / MB91F133 have a 254-KB (2 Mbit) capacity and feature a FLASH memory that can write each half-word (16 bits) using the FR-CPU, delete individual sectors sector and delete groups of sectors together using a single 3-V power source. * Outline of FLASH Memory This is a built-in 3-V 254-KB FLASH memory. This FLASH memory is the same as our 2-Mbit (256 K x 8 / 128 K x 16) FLASH memory MBM29LV400C and writing is possible from outside the device using a ROM writer. If used as a built-in ROM of the FR-CPU, as well as having an equivalent function to the MBM29LV400C, instructions / data can be read per word (32 bits) and high-speed operation of the device can be realized. Refer to the MBM29LV400C data sheet as well as this manual. The following functions can be realised in MB91FV130 / MB91F133 by combining the FLASH memory macro and FR-CPU interface circuits. * Functioning as memory for CPU program / data storage Access is possible with 32-bit bus width when used as ROM Reading / writing and erasing (automatic program algorithm *) are possible using CPU * MBM29LV400C-equivalent function of single FLASH memory products Reading / writing and erasing (automatic program algorithm *) are possible using ROM writer A case where this FLASH memory is used from FR-CPU is described in this section. Refer to the ROM writer manual separately for details if this FLASH memory is used from ROM writer. * : Automatic program algorithm = Embedded Algorithm TM Embedded Algorithm TM is the trademark of Advanced Micro Device. * Block Diagram
Rising edge detection
RDY/BUSY
Control signal generation
RESET BYTE OE
FLASH memory 2 Mbit (254 K x 8/127 K x 16)
WE CE Interruption request Bus control signal FA18 - 0 DI15 - 0 DO31 - 0
INTE
RDYINT
RDY
WE
Address buffer CA18 - 0
Data buffer CD31 - 0
FR-C bus (instruction / data)
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MB91133/MB91F133
* Memory Map FLASH memory mode and CPU mode for address mapping of FLASH memory are different. Mapping under each mode is shown as follows. * Memory map in FLASH memory mode
0FFFFFH
SA9 SA8 SA7 2 M-FLASH Memory image SA6 SA5 SA4 SA3
0C0000H
SA2 SA1 SA0 ( SAn : sector address n )
010000H
000000H
* Memory map in CPU memory mode
0FFFFFH
0FFFFFH 0F8000H
SA4
SA9
SA3 0F4000H FLASH memory area 0F0000H SA1 SA2
SA8 SA7 SA6
0C0800H RAM area 2 KByte 0C0000H
0E0000H SA0 SA5
( SAn : sector address n )
0007C0H 000000H
Status register
0C0800H 0C0000H
CPU mode
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MB91133/MB91F133
* Sector address table Sector Address SA5 SA6 SA7 SA8 SA9 SA0 SA1 SA2 SA3 SA4 Address Area 000C0802, 3h to 000DFFFE, Fh (LSB side 16 bit) 000E0002, 3h to 000EFFFE, Fh (LSB side 16 bit) 000F0002, 3h to 000F3FFE, Fh (LSB side 16 bit) 000F4002, 3h to 000F7FFE, Fh (LSB side 16 bit) 000F8002, 3h to 000FFFFE, Fh (LSB side 16 bit) 000C0800, 1h to 000DFFFC, Dh (MSB side 16 bit) 000E0000, 1h to 000EFFFC, Dh (MSB side 16 bit) 000F0000, 1h to 000F3FFC, Dh (MSB side 16 bit) 000F4000, 1h to 000F7FFC, Dh (MSB side 16 bit) 000F8000, 1h to 000FFFFC, Dh (MSB side 16 bit) Position of bit handled bit 15 to 0 bit 15 to 0 bit 15 to 0 bit 15 to 0 bit 15 to 0 bit 31 to 16 bit 31 to 16 bit 31 to 16 bit 31 to 16 bit 31 to 16 Sector Capacity 63 Kbyte 32 Kbyte 8 Kbyte 8 Kbyte 16 Kbyte 63 Kbyte 32 Kbyte 8 Kbyte 8 Kbyte 16 Kbyte
* Registers of FLASH Memory There are two types of FLASH memory registers, namely status register (FLCL) and wait register (FWTC). * Status Register (FLCR) (CPU mode) This register indicates the operation status of the FLASH memory. It controls interruption to the CPU and writing to the FLASH memory. Access is possible only in CPU mode. This register must not be accessed under Read / Modify / Write instructions.
bit 7 bit 6 RDYINT R/W (0) bit 5 WE R/W (0) bit 4 RDY R (X) bit 3 (X) bit 2 (X) bit 1 (X) bit 0 LPM R/W (0)
0007C0H
INTE R/W (0)
* Wait Register ( FWTC) Carries out wait control of the FLASH memory in CPU mode. Also, controls access to high-speed reading (33MHz) of FLASH memory. Configuration of Wait Register (FWTC) is as follows :
bit 7 bit 6 () bit 5 () bit 4 () bit 3 () bit 2 FACH W (0) bit 1 WTC1 R/W (0) bit 0 WTC0 R/W (0) ()
0007C4H
Note : FACH bit should be set to 1 or WTC1/0 should be set to 01b to operate machine clocks of CPUs exceeding 25 MHz.
87
MB91133/MB91F133
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -55 Max. VSS + 6.5 VSS + 3.8 VSS + 6.5 VSS + 6.5 VCC5 + 0.3 VCC3 + 0.3 AVCC + 0.3 VCC5 + 0.3 10 4 100 50 -10 -4 -50 -20 500 +150 (VSS = AVSS = 0.0 V) Symbol VCC5 VCC3 AVCC AVRH VI5 VI3 VIA VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD Tstg Unit V V V V V V V V mA mA mA mA mA mA mA mA mW C *4 *4 *2 *3 *2 *3 X0, X1, X0A, X01A *1 *1 Remarks
Parameter Power voltage Power voltage Analog power voltage Standard analog voltage Input voltage Input voltage Analog pin input voltage Output voltage Maximum "L" level output current Average "L" level output current Maximum total "L" level output current Average "L" level total output current Maximum "H" level output current Average "H" level output current Maximum total "H" level output current Average "H" level total output current Electricity consumption Storage temperature
*1 : Care must be taken that this does not exceed VCC5 + 0.3 V when the power is turned on. Also, care must be taken that AVCC does not exceed VCC5 when the power is turned on. AVCC should be set at the same electrical potential as VCC5. *2 : Peak value of the pin concerned is regulated as the maximum output current. *3 : Average current within 100 ms flowing in the pin concerned is regulated as the average output current. *4 : Average current within 100 ms flowing in all pins concerned is regulated as the average total output current. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB91133/MB91F133
2. Recommended Operating Conditions
Value Min. 4.5 3.0 3.0 2.7 2.7 VSS + 4.5 AVSS - 0.3 0 -40 Max. 5.5 3.6 3.6 3.6 3.6 VSS + 5.5 AVCC +70 +70
(VSS = AVSS = 0.0 V) Unit V V V V V V C C In external ROM external bus / internal ROM external bus modes In single-chip mode Remarks Under normal operation Under normal operation RAM status kept in the case of stop Under normal operation RAM status kept in the case of stop
Parameter Common Power voltage EVA FLASH MASK ROM Analog power voltage Standard analog voltage Operating temperature
Symbol VCC5 VCC3 VCC3 AVCC AVRH TA TA
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB91133/MB91F133
3. DC Characteristics
(MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value ReSymPin name Conditions Unit Parameter marks bol Min. Typ. Max. "H" level input voltage VIH VIHS VIL VILS VOH VOL ILI Input excluding following (*1) *1 Hysteresis input pin Input excluding following (*1) *1 Hysteresis input pin RST VCC5 VCC3 VCC5 VCC3 VCC5 VCC3 VCC3 VCC3 Other than VCC, AVCC, AVSS, AVRH and VSS VCC5 = 5.0 V, IOH = -4.0 mA VCC5 = 5.0 V, IOL = 4.0 mA VCC5 = 5.0 V, VSS < VI < VDD VCC5 = 5.0 V VCC3 = 3.0 V VCC5 = 5.0 V VCC3 = 3.0 V VCC5 = 5.0 V, TA = 25 C VCC3 = 3.0 V, TA = 25 C VCC3 = 3.3 V VCC3 = 3.3 V 0.7 VCC5 VCC5 - 0.4 VSS - 0.3 VSS - 0.3 2.6 -5 50 15 50 15 24 10 10 80 50 10 VCC5 + 0.3 VCC5 + 0.3 0.2 VCC5 VSS + 0.4 0.6 5 20 100 20 85 100 100 120 90 V V V V V V A k mA mA mA mA A A mA mA pF *3 *2 *2
"L" level input voltage "H" level output voltage "L" level output voltage Input leak current
Pull up RPULL resistance value ICC5 ICC3 ICCS5 Power current ICCS3 ICCH5 ICCH3 Power current (FLASH models) Input capacity ICC3 ICCS3 CIN
*1 : Refer to "PIN FUNCTION DESCRIPTIONS" *2 : In case of CLK pin output only (CL = 80 pF) *3 : Output pin OPEN
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MB91133/MB91F133
4. AC Characteristics
(1) Clock Timing Standard (MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value SymCondiParameter Pin name Unit Remarks bol tions Min. Max. Clock frequency (high-speed, self-oscillation) Clock frequency (high-speed, PLL usage) Clock frequency (low-speed) Clock cycle time Frequency fluctuation rate *1 (when PLL locked) CPU system Internal operation clock frequency Bus system Peripheral system CPU system Internal operation clock cycle time Bus system Peripheral system Self oscillation available area PLL usable area by self-oscillation input Self oscillation
fC
X0, X1
9
16.5
MHz
fCA tC f fCP fCPB
X0A, X1A
32 30.3 0.032 0.032 0.032 31250 10 33 25 25 25 31250 31250 31250 1000
kHz ns %
MHz Excluding analog area *2 Analog area *2
fCPP tCP tCPB
1 30.3 40 40 40
ns Excluding analog area *2 Analog area *2
tCPP
*1 : Frequency fluctuation rate indicates the maximum fluctuation ratio from the setting central frequency during locking in case of doubling. *2 : The targeted analog areas are the A/D and level comparator.
91
MB91133/MB91F133
-
f =
|| fO
x100 (%)
Central frequency fO -
tC VCC3 0.8 VCC3 0.2 VCC3 VSS
Peripheral system clock setting permitted area (A/D, D/A level comparator : 5 V 10%) < FLASH model >
VCC3 VCC3
< MASK ROM model >
Guaranteed operating range Power voltage (V) Power voltage (V) 3.6 3.6
Guaranteed operating range
3.0 fCPP
fCP
fCP 2.7 fCPP
32 K 1 M
25 M 33 M
32 K 1 M
25 M 33 M
Frequency (Hz)
Frequency (Hz)
92
MB91133/MB91F133
The relationship between the internal clock set by the CHC/CCK1/CCK0 bit of the Gear Control Register (GCR) and X0 input is as follows. X0 input * Original oscillation x 1 (CHC bit of GCR : 0 setting) (a) Gear x 1 Internal clock CCK1/0 : 00 (b) Gear x 1/2 Internal clock CCK1/0 : 01 (c) Gear x 1/4 Internal clock CCK1/0 : 10 (d) Gear x 1/8 Internal clock CCK1/0 : 11 * Original oscillation x 1/2 (CHC bit of GCR : 1 setting) (a) Gear x 1 Internal clock CCK1/0 : 00 (b) Gear x 1/2 Internal clock CCK1/0 : 01 (c) Gear x 1/4 Internal clock CCK1/0 : 10 (d) Gear x 1/8 Internal clock CCK1/0 : 11
tCYC tCYC
tCYC
tCYC
tCYC
tCYC
tCYC
tCYC
93
MB91133/MB91F133
(2) Reset Input Standards (MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value Pin CondiParameter Symbol Unit Remarks name tions Min. Max. Reset input time tRSTL RST tCP x 5 ns
tRSTL
RST
0.2 VCC
(3) Power On Reset (MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value SymPin Parameter Conditions Unit Remarks bol name Min. Max. Power startup time Power cut time Waiting time for oscillation stabilization fR tOFF tOSC VCC 2 213 tC 20 ms ms ns
tR
tOFF 0.9 x VCC3
VhhR
0.2 V
If the power voltage is changed rapidly, "Power On Reset" may be initiated. To start up smoothly, controlling any voltage fluctuations that may occur during operation is recommended.
VCC
Holding RAM data
Controling inclination at initiation to 50 mV/ms or less is recommended.
VSS
VCC
tOSC (waiting for oscillation stabilization)
RST
tRSTL
When power is turned on, start while the RST pin is set to "L" level, after which wait for tRSTL minutes and change the level to "H" once the VCC power level is reached.
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MB91133/MB91F133
(4) Serial I/O (CH0 to 4) (MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value Pin Parameter Symbol Conditions Unit Remarks name Min. Max. Serial clock cycle time SCK SO delay time Valid SI SCK SCK Valid SI holding time Serial clock H pulse width Serial clock L pulse width SCK SO delay time Valid SI SCK SCK Valid SI holding time Serial busy period SCS SCK, SO delay time SCS SCK input MASK time SCS SCK, SO Hi-Z time tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX tBUSY tCLZO tCLSL tCHOZ External clock Internal clock 8 tCPP -10 50 50 4 tCPP - 10 4 tCPP - 10 0 50 50 50 50 50 6 tCPP 50 3 tCPP ns ns ns ns ns ns ns ns ns ns ns ns ns *
*: Will be Min. 1 tCPP - 10 if pre-scalar setting is CS2, 1, 0 = 000. Internal shift clock mode
tSCYC
SCK
tSLOV
SO SI
tIVSH tSHIX
External shift clock mode
tCLZO tSLSH tSHSL tBUSY tCHOZ
SCK
tSLOV
SO SI
tIVSH tSHIX
SCS
tCLSL
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MB91133/MB91F133
(5) External Bus Measurement Conditions The following conditions apply to items without specific regulations. * Alternating current standard measurement condition VCC : 5.0 V 10%
Input VCC
VIH VIL VOH VOL
Output
VIH VIL
2.4 V 0.8 V
VOH VOL
2.4V 0.8V
0V
(Rise/fall time of input is 10 ns or less)
* Load condition
Output pin
C = 50 pF ( VCC : 5.0 V 10% )
* Load capacity - Delay time characteristic (Internally-based output delay)
[nS] 35 30 25 20 15 5 V Rise 10 5 0 0 20 40 50 60 80 100 120 C[pF] 5 V Fall
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MB91133/MB91F133
(6) Normal Bus Access Read/Write Operation (MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value SymParameter Pin name Conditions Unit Remarks bol Min. Max. Address delay time Data delay time RD delay time RD delay time WR0 to 1 delay time WR0 to 1 delay time Valid address / valid data input time RD valid data input time Data setup RD time RD Data holding time tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV tDSRH tRHDX RD D31 to D16 CLK A23 to A00 CLK D31 to D16 CLK RD CLK WR0 to 1 A23 to A00 D31 to D16 15 0 15 15 10 10 10 10 3/2x tCYC - 25 tCYC - 15 ns ns ns ns ns ns ns ns ns ns *1, *2 *1
*1 : Time (tCYC x number of cycles extended) needs to be added to this standard if the bus is extended by automatic waiting insertion and RDY input. *2 : Values of this standard are in case of gear cycle x 1. If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. * Calculation formula : (2 - n / 2) x tCYC - 25
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MB91133/MB91F133
tCYC BA1 VOH BA2 VOH VOL
CLK
VOL
tCHAV VOH VOL VOH VOL
A24 - A00
tCLRL
tCLRH
RD
VOH VOL
tRLDV tRHDX tAVDV VIH VIL tDSRH VIH VIL
D31 - D16
Read
tCLWL
tCLWH VOH
WR0 - WR1
VOL
tCHDV
D31 - D16
VOH VOL
Write
VOH VOL
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MB91133/MB91F133
(7) Ready Input Timing (MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value Pin Parameter Symbol Conditions Unit Remarks name Min. Max. RDY setup time CLK CLK RDY holding time tRDYS tRDYH RDY CLK RDY CLK 15 0 ns ns
tCYC
VOH
VOH VOL VOL
CLK
tRDYS
tRDYH
tRDYS tRDYH
RDY If "wait" is executed
VIL
VIH
RDY If "wait" is not executed
VIH
VIL
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MB91133/MB91F133
(8) Holding timing (MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value Pin Parameter Symbol Conditions Unit Remarks name Min. Max. BGRNT delay time BGRNT delay time Pin floating BGRNT time BGRNT Pin valid time tCHBGL tCHBGH tXHAL tHAHV CLK BGRNT BGRNT tCYC - 10 tCYC - 10 6 6 tCYC + 10 tCYC + 10 ns ns ns ns
Note : It takes at least one cycle from loading the BRQ to when BGRNT is changed.
tcyc
VOH
VOH
VOH
VOH
CLK
BRQ
tCHBGL
tCHBGH
BGRNT
VOH VOL
tXHAL
tHAHV
Each pin
High impedance
100
MB91133/MB91F133
(9) DMA Controller Timing (MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value Parameter Symbol Pin name Conditions Unit Remarks Min. Max. DREQ input pulse width DACK delay time (Normal bus) EOP delay time (Normal bus) DACK delay time EOP delay time tDRWH tCLDL tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH DREQ0 to DREQ2 CLK DACK0 to DACK2 CLK EOP0 to EOP2 CLK DACK0 to DACK2 CLK EOP0 to EOP2 2 tCYC 6 6 6 6 n / 2 x tCYC 6 n / 2 x tCYC 6 ns ns ns ns ns ns ns ns ns
tcyc
VOH
CLK
VOH VOL VOL tCLDH tCLEH
tCLDL tCLEL
DACK0 - 2 EOP0 - 2 (Normal bus)
VOH VOL
tCHDH
DACK0 - 2 EOP0 - 2
tCHDL tCHEL
VOH VOL
tDRWH
DREQ0 - 2
VIH
VIH
101
MB91133/MB91F133
5. A/D Transition
(MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value ReSymPin Conditions Unit Parameter marks bol name Min. Typ. Max. Resolution Conversion time Total tolerance Straight-line tolerance Differential straight-line tolerance Zero transition tolerance Full-scale transition tolerance Analog input current Analog input voltage Standard voltage Power current Standard voltage current supplied When conversion is activated When conversion is stopped When conversion is activated When conversion is stopped VOT VFST IAIN VAIN AVRH IA AVCC IAH IR AVRH IRH AN0 to AN7 AVCC = 5.0 V AVCC = 5.0 V, AVRH = 5.0V 2.0 5.0 3.0 10 4 A mA A LSB AVCC = 5.0 V, AVRH = 5.0 V 5.0 -4.0 -3.5 -2.0 4.0 3.5 2.0 10 Bit s LSB LSB LSB
AN0 to AVSS-1.5 AVSS+0.5 AVSS+2.5 LSB AN7 AVCC = 5.0 V, AN0 to AVRH = 5.0 V AVRH - 5.5 AVRH - 1.5 AVRH + 0.5 LSB AN7 AN0 to AN7 AN0 to AN7 AVRH AVSS 3.0 AVRH AVCC 5.0 V V mA 0.1 10 A
Tolerance between channels
Notes : * As the |AVRH| becomes smaller, the tolerance becomes larger. * Output impedance of external circuits other than analog input must be used if output impedance of external circuits < approx. 7 k If the output impedance of the external circuits is too high, the sampling time for the analog voltage may be insufficient. (Sampling time = 1.6 s at 33 MHz)
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MB91133/MB91F133
* Definition of A/D Converter Terms * Resolution : Analog changes that can be identified by A/D converter * Straight-line tolerance : Difference between the straight line linking the zero transition point (00 0000 0000 00 0000 0001) to the full-scale transition point (11 1111 1110 11 1111 1111) and actual conversion characteristics. * Differential straight-line tolerance : Difference compared to the ideal input voltage value required to change the output code 1 LSB * Total tolerance : Indicates the difference between the actual and theoretical values and includes zero transition tolerance, fullscale transition tolerance, and straight-line tolerance.
Total tolerance
3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB ( N - 1 ) + 0.5 LSB} 1.5 LSB
004 003 002 001 0.5 LSB AVSS AVRH Analog input VNT (Actual measured value) Actual conversion characteristics Ideal characteristics
Total tolerance of digital output N = 1 LSB (Ideal value) =
VNT - {1 LSB x (N - 1) + 0.5 LSB'} 1 LSB [V] [V] VNT : Voltage of digital output transferred from (N + 1) to N
AVRH - AVSS 1024
VOT (Ideal value) = AVSS + 0.5 LSB'
VFST (Ideal value) = AVRH - 1.5 LSB' [V]
(Continued)
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MB91133/MB91F133
(Continued)
Straight-line tolerance
3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB ( N - 1 ) + VOT} VFST (Actual measured value) N+1 Actual conversion characteristics
Differential straight-line tolerance
Digital output
N
Ideal characteristics
004 003 002 001 VOT (Actual measured value) AVSS Analog input AVRH VNT (Actual measured value) Actual conversion characteristics Ideal characteristics
N-1
N-2
VFST (Actual measured VNT value) (Actual measured value) Actual conversion characteristics Analog input AVRH
AVSS
Straight-line tolerance = VNT - {1 LSB x (N - 1) + VOT} 1 LSB of digital output N Differential straight-line tolerance = of digital output N 1LSB (Ideal value) = V (N + 1) T - VNT 1 LSB VFST - VOT 1022 [V] -1
[LSB]
[LSB]
VOT : Voltage with digital output transferred from (000) H to (001) H VFST : Voltage with digital output transferred from (3FE) H to (3FF) H
6. D/A Transition
(MASK Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) (FLASH Model VCC5 = AVCC = DAVC = 5.0 V 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = -40 C to +70 C) Value Pin CondiReParameter Symbol Unit name tions marks Min. Typ. Max. Resolution Differential straight-line tolerance Conversion time Analog output impedance 10 28 8 0.9 20 Bit LSB s k *
*: CL = 20 PF 104
MB91133/MB91F133
s INSTRUCTIONS (165 INSTRUCTIONS)
1. How to Read Instruction Set Summary
Mnemonic ADD * ADD Rj, Ri #s5, Ri , , (2) Type A C , , (3) OP A6 A4 , , (4) CYC 1 1 , , (5) NZVC CCCC CCCC , , (6) Operation Ri + Rj Ri Ri + s5 Ri , , (7) Remarks
(1)
(1) Names of instructions Instructions marked with * are not included in CPU specifications. These are extended instruction codes added/extended at assembly language levels. (2) Addressing modes specified as operands are listed in symbols. Refer to "2. Addressing mode symbols" for further information. (3) Instruction types (4) Hexa-decimal expressions of instructions (5) The number of machine cycles needed for execution a: Memory access cycle and it has possibility of delay by Ready function. b: Memory access cycle and it has possibility of delay by Ready function. If an object register in a LD operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or if the instruction belongs to instruction format A group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. For a, b, c and d, minimum execution cycle is 1. (6) Change in flag sign * Flag change C : Change - : No change 0 : Clear 1 : Set * Flag meanings N : Negative flag Z : Zero flag V : Over flag C : Carry flag (7) Operation carried out by instruction
105
MB91133/MB91F133
2. Addressing Mode Symbols
: Register direct (R0 to R15, AC, FP SP) , : Register direct (R0 to R15, AC, FP SP) , : Register direct (R13, AC) : Register direct (Program status register) : Register direct (TBR, RP SSP USP MDH, MDL) , , , : Register direct (CR0 to CR15) : Register direct (CR0 to CR15) : Unsigned 8-bit immediate (-128 to 255) Note: -128 to -1 are interpreted as 128 to 255 #i20 : Unsigned 20-bit immediate (-0X80000 to 0XFFFFF) Note: -0X7FFFF to -1 are interpreted as 0X7FFFF to 0XFFFFF #i32 : Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF) Note: -0X80000000 to -1 are interpreted as 0X80000000 to 0XFFFFFFFF #s5 : Signed 5-bit immediate (-16 to 15) #s10 : Signed 10-bit immediate (-512 to 508, multiple of 4 only) #u4 : Unsigned 4-bit immediate (0 to 15) #u5 : Unsigned 5-bit immediate (0 to 31) #u8 : Unsigned 8-bit immediate (0 to 255) #u10 : Unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : Unsigned 8-bit direct address (0 to 0XFF) @dir9 : Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only) @dir10 : Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only) label9 : Signed 9-bit branch address (-0X100 to 0XFC, multiple of 2 only) label12 : Signed 12-bit branch address (-0X800 to 0X7FC, multiple of 2 only) label20 : Signed 20-bit branch address (-0X80000 to 0X7FFFF) label32 : Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF) @Ri : Register indirect (R0 to R15, AC, FP SP) , @Rj : Register indirect (R0 to R15, AC, FP SP) , @(R13, Rj) : Register relative indirect (Rj: R0 to R15, AC, FP SP) , @(R14, disp10) : Register relative indirect (disp10: -0X200 to 0X1FC, multiple of 4 only) @(R14, disp9) : Register relative indirect (disp9: -0X100 to 0XFE, multiple of 2 only) @(R14, disp8) : Register relative indirect (disp8: -0X80 to 0X7F) @(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only) @Ri+ : Register indirect with post-increment (R0 to R15, AC, FP SP) , @R13+ : Register indirect with post-increment (R13, AC) @SP+ : Stack pop @-SP : Stack push (reglist) : Register list Ri Rj R13 Ps Rs CRi CRj #i8
106
MB91133/MB91F133
3. Instruction Types
MSB 16 bits OP 8 Rj 4 Ri 4 LSB
Type A
Type B
OP 4
i8/o8 8
Ri 4
Type C
OP 8
u4/m4 4
Ri 4
ADD, ADDN, CMP, LSL, LSR and ASR instructions only Type *C' OP 7 s5/u5 5 Ri 4
Type D
OP 8
u8/rel8/dir/reglist 8
Type E
OP 8
SUB-OP 4
Ri 4
Type F
OP 5
rel11 11
107
MB91133/MB91F133
4. Detailed Description of Instructions
* Add/subtract operation instructions (10 instructions) Mnemonic ADD * ADD ADD ADD2 ADDC ADDN * ADDN ADDN ADDN2 SUB SUBC SUBN Rj, Ri #s5, Ri #i4, Ri #i4, Ri Rj, Ri Rj, Ri #s5, Ri #i4, Ri #i4, Ri Rj, Ri Rj, Ri Rj, Ri
Type
OP A6 A4 A4 A5 A7 A2 A0 A0 A1 AC AD AE
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1
Operation
Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension Add operation with sign MSB is interpreted as a sign in assembly language Zero-extension Sign-extension
A C' C C A A C' C C A A A
C C C C Ri + Rj Ri C C C C Ri + s5 Ri C C C C Ri + extu (i4) Ri C C C C Ri + extu (i4) Ri C C C C Ri + Rj + c Ri - - - - Ri + Rj Ri - - - - Ri + s5 Ri - - - - Ri + extu (i4) Ri - - - - Ri + extu (i4) Ri C C C C Ri - Rj Ri C C C C Ri - Rj - c Ri - - - - Ri - Rj Ri
Subtract operation with carry
* Compare operation instructions (3 instructions) Mnemonic CMP * CMP CMP CMP2 Rj, Ri #s5, Ri #i4, Ri #i4, Ri
Type
OP AA A8 A8 A9
Cycle N Z V C 1 1 1 1
Operation
Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension
A C' C C
C C C C Ri - Rj C C C C Ri - s5 C C C C Ri + extu (i4) C C C C Ri + extu (i4)
* Logical operation instructions (12 instructions) Mnemonic AND AND ANDH ANDB OR OR ORH ORB EOR EOR EORH EORB Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri
Type
OP 82 84 85 86 92 94 95 96 9A 9C 9D 9E
Cycle N Z V C 1 1 + 2a 1 + 2a 1 + 2a 1 1 + 2a 1 + 2a 1 + 2a 1 1 + 2a 1 + 2a 1 + 2a CC CC CC CC CC CC CC CC CC CC CC CC - - - - - - - - - - - - - - - - - - - - - - - - Ri & (Ri) & (Ri) & (Ri) & Ri (Ri) (Ri) (Ri) | | | |
Operation = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj
Remarks Word Word Half word Byte Word Word Half word Byte Word Word Half word Byte
A A A A A A A A A A A A
Ri ^ (Ri) ^ (Ri) ^ (Ri) ^
108
MB91133/MB91F133
* Bit manipulation arithmetic instructions (8 instructions) Mnemonic BANDL BANDH * BAND BORL BORH * BOR BEORL BEORH * BEOR BTSTL BTSTH #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH)
Type
OP 80 81
Cycle N Z V C
Operation
Remarks Manipulate lower 4 bits Manipulate upper 4 bits
C C *1 C C *2 C C *3 C C
1 + 2a - - - - (Ri) & = (F0H + u4) 1 + 2a - - - - (Ri) & = ((u4<<4) + 0FH) - - - - - (Ri) & = u8
90 91
1 + 2a - - - - (Ri) | = u4 1 + 2a - - - - (Ri) | = (u4<<4) - - - - - (Ri) | = u8
Manipulate lower 4 bits Manipulate upper 4 bits
98 99
1 + 2a - - - - (Ri) ^ = u4 1 + 2a - - - - (Ri) ^ = (u4<<4) - - - - - (Ri) ^ = u8 0 C - - (Ri) & u4 C C - - (Ri) & (u4<<4)
Manipulate lower 4 bits Manipulate upper 4 bits
88 89
2+a 2+a
Test lower 4 bits Test upper 4 bits
*1: Assembler generates BANDL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BANDH if "u8&0xF0" leaves an active bit. Depending on the value in the "u8" format, both BANDL and BANDH may be generated. *2: Assembler generates BORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BORH if "u8&0xF0" leaves an active bit. *3: Assembler generates BEORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BEORH if "u8&0xF0" leaves an active bit. * Add/subtract operation instructions (10 instructions) Mnemonic MUL MULU MULH MULUH DIVOS DIVOU DIV1 DIV2 DIV3 DIV4S * DIV * DIVU Rj, Ri Rj, Ri Rj, Ri Rj, Ri Ri Ri Ri Ri Ri Ri *1 *2
Type
OP AF AB BF BB 97 - 4 97 - 5 97 - 6 97 - 7 9F - 6 9F - 7
Cycle N Z V C 5 5 3 3 1 1 d 1 1 1 - - CCC CCC CC- CC- - - - - - - - - - C C - - C - - - - - - - - - - -
Operation Rj x Ri MDH, MDL Rj x Ri MDH, MDL Rj x Ri MDL Rj x Ri MDL
Remarks 32-bit x 32-bit = 64-bit Unsigned 16-bit x 16-bit = 32-bit Unsigned Step calculation 32-bit/32-bit = 32-bit
A A A A E E E E E E
- - C C - - C MDL/Ri MDL, MDL%Ri MDH - C - C MDL/Ri MDL, MDL%Ri MDH
Unsigned
*1: DIVOS, DIV1 x 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes. *2: DIVOU and DIV1 x 32 are generated. A total instruction code length of 66 bytes.
109
MB91133/MB91F133
* Shift arithmetic instructions (9 instructions) Mnemonic LSL * LSL LSL LSL2 LSR * LSR LSR LSR2 ASR * ASR ASR ASR2 Rj, Ri #u5, Ri #u4, Ri #u4, Ri Rj, Ri #u5, Ri #u4, Ri #u4, Ri Rj, Ri #u5, Ri #u4, Ri #u4, Ri
Type
OP B6 B4 B4 B5 B2 B0 B0 B1 BA B8 B8 B9
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 CC CC CC CC CC CC CC CC CC CC CC CC - - - - - - - - - - - - C C C C C C C C C C C C
Operation Ri<>Rj Ri Ri>>u5 Ri Ri>>u4 Ri Ri>>(u4 + 16) Ri Ri>>Rj Ri Ri>>u5 Ri Ri>>u4 Ri Ri>>(u4 + 16) Ri
Remarks Logical shift
A C' C C A C' C C A C' C C
Logical shift
Logical shift
* Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) Mnemonic LDI: 32 LDI: 20 LDI: 8 * LDI #i32, Ri #i20, Ri #i8, Ri # {i8 | i20 | i32}, Ri *1
Type
OP 9F - 8 9B C0
Cycle N Z V C 3 2 1
Operation
Remarks Upper 12 bits are zeroextended Upper 24 bits are zeroextended
E C B
- - - - i32 Ri - - - - i20 Ri - - - - i8 Ri {i8 | i20 | i32} Ri
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. If an immediate value contains relative value or external reference, assembler selects i32. * Memory load instructions (13 instructions) Mnemonic LD LD LD LD LD LD LD LDUH LDUH LDUH LDUB LDUB LDUB @Rj, Ri @(R13, Rj), Ri @(R14, disp10), Ri @(R15, udisp6), Ri @R15 +, Ri @R15 +, Rs @R15 +, PS @Rj, Ri @(R13, Rj), Ri @(R14, disp9), Ri @Rj, Ri @(R13, Rj), Ri @(R14, disp8), Ri
Type
OP 04 00 20 03 07 - 0 07 - 8 07 - 9 05 01 40 06 02 60
Cycle N Z V C b b b b b b
1+a+b
Operation (Rj) Ri (R13 + Rj) Ri (R14 + disp10) Ri (R15 + udisp6) Ri (R15) Ri, R15 + = 4 (R15) Rs, R15 + = 4
Remarks
A A B C E E E A A B A A B
- - - - - -
- - - - - -
- - - - - -
- - - - - -
C C C C (R15) PS, R15 + = 4 - - - - (Rj) Ri - - - - (R13 + Rj) Ri - - - - (R14 + disp9) Ri - - - - (Rj) Ri - - - - (R13 + Rj) Ri - - - - (R14 + disp8) Ri
Rs: Special-purpose register Zero-extension Zero-extension Zero-extension Zero-extension Zero-extension Zero-extension
b b b b b b
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 o8 = disp8:Each disp is a code extension. disp9 o8 = disp9>>1:Each disp is a code extension. disp10 o8 = disp10>>2:Each disp is a code extension. udisp6 u4 = udisp6>>2:udisp4 is a 0 extension. 110
MB91133/MB91F133
* Memory store instructions (13 instructions) Mnemonic ST ST ST ST ST ST ST STH STH STH STB STB STB Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp10) Ri, @(R15, udisp6) Ri, @-R15 Rs, @-R15 PS, @-R15 Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp9) Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp8)
Type
OP 14 10 30 13 17 - 0 17 - 8 17 - 9 15 11 50 16 12 70
Cycle N Z V C a a a a a a a a a a a a a - - - - - - - - - - - - - - - - - - - - - - - -
Operation Ri (Rj) Ri (R13 + Rj) Ri (R14 + disp10) Ri (R15 + usidp6) R15 - = 4, Ri (R15) R15 - = 4, Rs (R15) Word Word Word
Remarks
A A B C E E E A A B A A B
- - - - R15 - = 4, PS (R15) - - - - Ri (Rj) - - - - Ri (R13 + Rj) - - - - Ri (R14 + disp9) - - - - Ri (Rj) - - - - Ri (R13 + Rj) - - - - Ri (R14 + disp8)
Rs: Special-purpose register Half word Half word Half word Byte Byte Byte
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 o8 = disp8:Each disp is a code extension. disp9 o8 = disp9>>1:Each disp is a code extension. disp10 o8 = disp10>>2:Each disp is a code extension. udisp6 u4 = udisp6>>2:udisp4 is a 0 extension. * Transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) Mnemonic MOV MOV MOV MOV MOV Rj, Ri Rs, Ri Ri, Rs PS, Ri Ri, PS
Type
OP 8B B7 B3 17 - 1 07 - 1
Cycle N Z V C 1 1 1 1 c
Operation
Remarks Transfer between general-purpose registers Rs: Special-purpose register Rs: Special-purpose register
A A A E E
- - - - Rj Ri - - - - Rs Ri - - - - Ri Rs - - - - PS Ri C C C C Ri PS
111
MB91133/MB91F133
* Non-delay normal branch instructions (23 instructions) Mnemonic JMP CALL CALL RET INT #u8 @Ri label12 @Ri
Type
OP 97 - 0 D0 97 - 1 97 - 2 1F
Cycle N Z V C 2 2 2 2 3+3a - - - - Ri PC
Operation
Remarks
E F E E D
- - - - PC + 2 RP , PC + 2 + rel11 x 2 PC - - - - PC + 2 RP Ri PC , - - - - RP PC - - - - SSP - = 4, PS (SSP), SSP - = 4, PC + 2 (SSP), 0 I flag, 0 S flag, (TBR + 3FC - u8 x 4) PC Return
INTE
E
9F - 3 3 + 3a - - - - SSP - = 4, PS (SSP), For emulator SSP - = 4, PC + 2 (SSP), 0 S flag, (TBR + 3D8 - u8 x 4) PC 97 - 3 2 + 2a C C C C (R15) PC, R15 - = 4, (R15) PS, R15 - = 4 E1 E0 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF 1 2 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Non-branch PC + 2 + rel8 x 2 PC PCif Z = = 1 PCif Z = = 0 PCif C = = 1 PCif C = = 0 PCif N = = 1 PCif N = = 0 PCif V = = 1 PCif V = = 0 PCif V xor N = = 1 PCif V xor N = = 0 PCif (V xor N) or Z = = 1 PCif (V xor N) or Z = = 0 PCif C or Z = = 1 PCif C or Z = = 0
RETI BNO BRA BEQ BNE BC BNC BN BP BV BNV BLT BGE BLE BGT BLS BHI label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9
E D D D D D D D D D D D D D D D D
Notes: * "2/1" in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. * The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 rel8 = (label9 - PC - 2)/2 label12 rel11 = (label12 - PC - 2)/2 * RETI must be operated while S flag = 0.
112
MB91133/MB91F133
* Branch instructions with delays (20 instructions) Mnemonic JMP:D CALL:D CALL:D RET:D BNO:D BRA:D BEQ:D BNE:D BC:D BNC:D BN:D BP:D BV:D BNV:D BLT:D BGE:D BLE:D BGT:D BLS:D BHI:D label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 @Ri label12 @Ri
Type
OP 9F - 0 D8 9F - 1 9F - 2 F1 F0 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Operation
Remarks
E F E E D D D D D D D D D D D D D D D D
- - - - Ri PC - - - - PC + 4 RP , PC + 2 + rel11 x 2 PC - - - - PC + 4 RP Ri PC , - - - - RP PC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Non-branch PC + 2 + rel8 x 2 PC PCif Z = = 1 PCif Z = = 0 PCif C = = 1 PCif C = = 0 PCif N = = 1 PCif N = = 0 PCif V = = 1 PCif V = = 0 PCif V xor N = = 1 PCif V xor N = = 0 PCif (V xor N) or Z = = 1 PCif (V xor N) or Z = = 0 PCif C or Z = = 1 PCif C or Z = = 0 Return
Notes: * The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 rel8 = (label9 - PC - 2)/2 label12 rel11 = (label12 - PC - 2)/2 * Delayed branch operation always executes next instruction (delay slot) before making a branch. * Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other instruction is stored, this device may operate other operation than defined. The instruction described "1" in the other cycle column than branch instruction. The instruction described "a", "b", "c" or "d" in the cycle column.
113
MB91133/MB91F133
* Direct addressing instructions Mnemonic DMOV DMOV DMOV DMOV DMOV DMOV DMOVH DMOVH DMOVH DMOVH DMOVB DMOVB DMOVB DMOVB @dir10, R13, @dir10, @R13+, @dir10, @R15+, @dir9, R13, @dir9, @R13+, @dir8, R13, @dir8, @R13+, R13 @dir10 @R13+ @dir10 @-R15 @dir10 R13 @dir9 @R13+ @dir9 R13 @dir8 @R13+ @dir8
Type
OP 08 18 0C 1C 0B 1B 09 19 0D 1D 0A 1A 0E 1E
Cycle N Z V C b a 2a 2a 2a 2a b a 2a 2a b a 2a 2a - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Operation (dir10) R13 R13 (dir10) (dir10) (R13), R13 + = 4 (R13) (dir10), R13 + = 4 R15 - = 4, (dir10) (R15) (R15) (dir10), R15 + = 4 (dir9) R13 R13 (dir9) (dir9) (R13), R13 + = 2 (R13) (dir9), R13 + = 2 (dir8) R13 R13 (dir8) (dir8) (R13), R13 + + (R13) (dir8), R13 + + Word Word Word Word Word Word
Remarks
D D D D D D D D D D D D D D
Half word Half word Half word Half word Byte Byte Byte Byte
Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from disp8 to disp10 are as follows: disp8 dir + disp8:Each disp is a code extension disp9 dir = disp9>>1:Each disp is a code extension disp10 dir = disp10>>2:Each disp is a code extension * Resource instructions (2 instructions) Mnemonic LDRES STRES @Ri+, #u4, #u4 @Ri+
Type
OP BC BD
Cycle N Z V C a a
Operation
Remarks u4: Channel number u4: Channel number
C C
- - - - (Ri) u4 resource Ri + = 4 - - - - u4 resource (Ri) Ri + = 4
* Co-processor instructions (4 instructions) Mnemonic COPOP COPLD COPST COPSV #u4, #CC, CRj, CRi #u4, #CC, Rj, CRi #u4, #CC, CRj, Ri #u4, #CC, CRj, Ri
Type
OP 9F - C 9F - D 9F - E 9F - F
Cycle N Z V C 2+a 1 + 2a 1 + 2a 1 + 2a - - - - - - - - - - - - - - - -
Operation Calculation Rj CRi CRj Ri CRj Ri
Remarks
E E E E
No error traps
114
MB91133/MB91F133
* Other instructions (16 instructions) Mnemonic NOP ANDCCR #u8 ORCCR #u8 STILM ADDSP EXTSB EXTUB EXTSH EXTUH LDM0 LDM1 * LDM STM0 STM1 * STM2 ENTER #u8 #s10 Ri Ri Ri Ri (reglist) (reglist) (reglist) (reglist) (reglist) (reglist) #u10 *5 *2 D 0F *3 D D 8E 8F *1
Type
OP 9F - A 83 93 87 A3 97 - 8 97 - 9 97 - A 97 - B 8C 8D
Cycle N Z V C 1 c c 1 1 1 1 1 1 *4 *4 - *
6
Operation
Remarks
E D D D D E E E E D D
- - - - No changes C C C C CCR and u8 CCR C C C C CCR or u8 CCR - - - - i8 ILM - - - - R15 + = s10 - - - - - - - - - - - - - - - - Sign extension 8 32 bits Zero extension 8 32 bits Sign extension 16 32 bits Zero extension 16 32 bits Load-multi R0 to R7 Load-multi R8 to R15 Load-multi R0 to R15 Store-multi R0 to R7 Store-multi R8 to R15 Store-multi R0 to R15 Entrance processing of function Exit processing of function For SEMAFO management Byte data Set ILM immediate value ADD SP instruction
- - - - (R15) reglist, R15 increment - - - - (R15) reglist, R15 increment - - - - (R15 + +) reglist, - - - - R15 decrement, reglist (R15) - - - - R15 decrement, reglist (R15) - - - - reglist (R15 + +) - - - - R14 (R15 - 4), R15 - 4 R14, R15 - u10 R15 - - - - R14 + 4 R15, (R15 - 4) R14 - - - - Ri TEMP , (Rj) Ri, TEMP (Rj)
*6 - 1+a
LEAVE XCHB @Rj, Ri
E A
9F - 9 8A
b 2a
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler description s10 is as follows. s10 s8 = s10>>2 *2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler description u10 is as follows. u10 u8 = u10>>2 *3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified, assembler generates LDM1. Both LDM0 and LDM1 may be generated. *4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following calculation; a x (n - 1) + b + 1 when "n" is number of registers specified. *5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified, assembler generates STM1. Both STM0 and STM1 may be generated. *6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following calculation; a x n + 1 when "n" is number of registers specified.
115
MB91133/MB91F133
* 20-bit normal branch macro instructions Mnemonic * CALL20 * BRA20 * BEQ20 * BNE20 * BC20 * BNC20 * BN20 * BP20 * BV20 * BNV20 * BLT20 * BGE20 * BLE20 * BGT20 * BLS20 * BHI20 label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri Operation Next instruction address RP label20 PC , label20 PC if (Z = = 1) then label20 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL20 (1) If label20 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL @Ri *2: BRA20 (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP @Ri *3: Bcc20 (BEQ20 to BHI20) (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP @Ri false:
116
MB91133/MB91F133
* 20-bit delayed branch macro instructions Mnemonic * CALL20:D label20, Ri * BRA20:D * BEQ20:D * BNE20:D * BC20:D * BNC20:D * BN20:D * BP20:D * BV20:D * BNV20:D * BLT20:D * BGE20:D * BLE20:D * BGT20:D * BLS20:D * BHI20:D label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri Operation Next instruction address + 2 RP label20 PC , label20 PC if (Z = = 1) then label20 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL20:D (1) If label20 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL:D @Ri *2: BRA20:D (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP:D @Ri *3: Bcc20:D (BEQ20:D to BHI20:D) (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP:D @Ri false:
117
MB91133/MB91F133
* 32-bit normal macro branch instructions Mnemonic * CALL32 * BRA32 * BEQ32 * BNE32 * BC32 * BNC32 * BN32 * BP32 * BV32 * BNV32 * BLT32 * BGE32 * BLE32 * BGT32 * BLS32 * BHI32 label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri Operation Next instruction address RP label32 PC , label32 PC if (Z = = 1) then label32 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL32 (1) If label32 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL @Ri *2: BRA32 (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP @Ri *3: Bcc32 (BEQ32 to BHI32) (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP @Ri false:
118
MB91133/MB91F133
* 32-bit delayed macro branch instructions Mnemonic * CALL32:D label32, Ri * BRA32:D * BEQ32:D * BNE32:D * BC32:D * BNC32:D * BN32:D * BP32:D * BV32:D * BNV32:D * BLT32:D * BGE32:D * BLE32:D * BGT32:D * BLS32:D * BHI32:D label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri Operation Next instruction address + 2 RP label32 PC , label32 PC if (Z = = 1) then label32 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL32:D (1) If label32 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL:D @Ri *2: BRA32:D (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP:D @Ri *3: Bcc32:D (BEQ32:D to BHI32:D) (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP:D @Ri false:
119
MB91133/MB91F133
s ORDERING INFORMATION
Part number MB91133PMT2-XXX MB91133PBT-XXX MB91F133PMT2 MB91F133PBT MB91FV130CR-ES Package 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic FBGA (BGA-144P-M01) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic FBGA (BGA-144P-M01) 299-pin ceramic PGA (PGA-299) Remarks
120
MB91133/MB91F133
s PACKAGE DIMENSIONS
144-pin plastic FBGA (BGA-144P-M01)
12.000.10(.472.004)SQ
Note) Corner shape may differ from the diagram.
1.25 -0.10 .049 -.004 (Mounting height) 0.380.10(.015.004) (Stand off)
+0.20
+.008
10.40(.409)REF 0.80(.031)TYP
14 13 12 11 10 9 8 7 6 0.10(.004) INDEX 5 4 3 2 1 PNMLKJHGFEDCBA C0.80(.031) 144-O0.450.10 (144-O.018.004) 0.08(.003)
M
C
1998 FUJITSU LIMITED B144001S-2C-2
Dimensions in mm (inches)
121
MB91133/MB91F133
144-pin plastic LQFP (FPT-144P-M08)
22.000.30(.866.012)SQ 20.000.10(.787.004)SQ 1.70(.67)MAX 0(0)MIN (STAND OFF)
108 109
73 72
17.50 (.686) REF INDEX
144 37
21.00 (.827) NOM
Details of "A" part 0.15(.006)
0.15(.006) 0.15(.006)MAX 0.40(.016)MAX "A"
LEAD No.
1
36
Details of "B" part
M
0.50(.0197)TYP
0.200.10 (.008.004)
0.08(.003)
0.150.05 (.006.002) 0 10
0.10(.004)
0.500.20(.020.008) "B"
C
1995 FUJITSU LIMITED F144019S-1C-2
Dimensions in mm (inches)
122
MB91133/MB91F133
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0101 (c) FUJITSU LIMITED Printed in Japan

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